fix debug signal
[Chiptunes-pms150c.git] / bsv.asm
CommitLineData
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1.area FUSE (ABS)
2.org 0x3ff*2
3.word ( 0x0260 | 1<<0 | 5<<2 | 1<<7 | 3<<10 )
4; reserved_bits | security_off | lvr_1v8 | io_drv_norm | boot_fast
5
ec2152ea 6.area OSEG (OVR,DATA)
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7notes: .ds 16 ; 0x00 .. 0x0f
8i0: .ds 1 ; 0x10
9i1: .ds 1 ; 0x11
10i2: .ds 1 ; 0x12
11n: .ds 1 ; 0x13
12.even ; make next two bytes word-aligned
13zero: .ds 1 ; 0x14
14tmp_1: .ds 1 ; 0x15
15tmp_hi: .ds 1 ; 0x16
16tmp_lo: .ds 1 ; 0x17
17pwm: .ds 1 ; 0x18
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18
19.even ; SP must be aligned
20stack_start: .ds 1
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21.area SSEG
22stack: .ds 1
23
24; aliases for memory locations:
25notes_ix = tmp_1
26t = tmp_1
27mul2 = tmp_hi
28mul1 = tmp_lo
29mod3hi = tmp_hi
30mod3lo = tmp_lo
31
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32; io addresses
33clkmd = 0x03
34inten = 0x04
35intrq = 0x05
36tm2c = 0x1C
37tm2b = 0x09
38tm2s = 0x17
39t16m = 0x06
40eoscr = 0x0A
41padier = 0x0D
42pa = 0x10
43pac = 0x11
44paph = 0x12
45misc = 0x1B
46gpcc = 0x1A
47ihrcr = 0x0B
48
49; Calibration Parameters:
50; Bitshift Variations calls for an 8kHz sample rate; with an interrupt every
51; 512 cycles (the next power of two above the 495 cycles the program needs for
52; execution), this gives us a clock speed of 512 * 8khz = 4.096MHz. The MCU
936a9ec2 53; will be powered by a 3V lithium coin cell.
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54calib_freq = 4096000 ; Hz
55calib_vdd = 3000 ; mV
56
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57; Clock Parameters:
58; during playback: IHRC/4, WDT off, keep ILRC on
59active_clock = (( 0<<5 | 1<<4 | 0<<3 | 1<<2 | 0<<1 | 0<<0 ))
60; during deep-sleep: ILRC/1, WDT off
61sleep_clock = (( 7<<5 | 1<<4 | 0<<3 | 1<<2 | 0<<1 | 0<<0 ))
62; for extra power saving, consider: 6<<5|0<<3 for ilrc/6, 2<<5|1<<3 for ilrc/16
63
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64; cycle count (worst-case)
65; mod3: 28
66; g: 81
67; sample: 115 + 4*g + 2*mod3 = 495
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68; isr overhead: 12
69; TOTAL: sample + overhead = 507
ec2152ea 70
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71; portA.4: audio out
72; portA.6: debug pin
73
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74
75.area CSEG (CODE,ABS)
ec2152ea 76.org 0x0000
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77 GOTO init
78
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79.org 0x0020
80 GOTO interrupt
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81
82mod3:
83 MOV a, mod3hi
84 ADD mod3lo, a ; mod3lo = hi+lo
85 MOV a, #0
86 ADDC a ; mod3hi, 1bit
87 SWAP a
88 MOV mod3hi, a
89
90 MOV a, mod3lo
91 SWAP a
92 AND a, #0xf ; (mod3lo>>4)
93 XCH mod3lo ; a=mod3lo, mod3lo=mod3lo>>4
94 AND a, #0xF ; a=mod3lo&0xf, mod3lo=mod3lo>>4
95 ADD a, mod3lo ; (mod3lo & 0xF)
96 ADD a, mod3hi
97 MOV mod3lo, a
98
99 AND a, #0x3 ; a = (mod3lo & 0x3)
100 SR mod3lo
101 SR mod3lo ; (mod3lo >> 2)
102 ADD a, mod3lo
103 MOV mod3lo, a
104
105 AND a, #0x3 ; a = (mod3lo & 0x3)
106 SR mod3lo
107 SR mod3lo ; (mod3lo >> 2)
108 ADD a, mod3lo
109
110 SUB a, #3
111 T0SN f, c
112 ADD a, #3
113 RET
114
115g:
116 ; notes_ix_hi = always 0
117 AND a, #0x7
118 MOV notes_ix, a
119 ; test i2 & 3:
120 MOV a, i2
121 AND a, #3
122 T0SN f, z
123 SET1 notes_ix, #3
124 IDXM a, notes_ix
125
126 MOV t, a
127 CLEAR mul2
128 CLEAR mul1
129 ; note: LSB of result (mul0) is not needed for our purposes
130 ;;1/8:
131 SR t
132 T1SN f, c
133 GOTO skip1
134 MOV a, i0
135 ADD mul1, a
136 MOV a, i1
137 ADDC mul2, a
138 skip1: SR mul2
139 SRC mul1
140 ;;2/8:
141 SR t
142 skip2: SR mul2
143 SRC mul1
144 ;;3/8:
145 SR t
146 T1SN f, c
147 GOTO skip3
148 MOV a, i0
149 ADD mul1, a
150 MOV a, i1
151 ADDC mul2, a
152 skip3: SR mul2
153 SRC mul1
154 ;;4/8:
155 SR t
156 T1SN f, c
157 GOTO skip4
158 MOV a, i0
159 ADD mul1, a
160 MOV a, i1
161 ADDC mul2, a
162 skip4: SR mul2
163 SRC mul1
164 ;;5/8:
165 SR t
166 T1SN f, c
167 GOTO skip5
168 MOV a, i0
169 ADD mul1, a
170 MOV a, i1
171 ADDC mul2, a
172 skip5: SR mul2
173 SRC mul1
174 ;;6/8:
175 SR t
176 T1SN f, c
177 GOTO skip6
178 MOV a, i0
179 ADD mul1, a
180 skip6:
181 SRC mul1
182 ;;7/8:
183 SR t
184 T1SN f, c
185 GOTO skip7
186 MOV a, i0
187 ADD mul1, a
188 skip7:
189 SRC mul1
190 ;;8/8:
191 SR t
192 T1SN f, c
193 GOTO skip8
194 MOV a, i0
195 ADD mul1, a
196 skip8:
197 SRC mul1
198
199 MOV a, mul1
200 RET
201
202init:
54babda0 203 ; clock setup:
a43c9c44 204 SET1 clkmd, #4 ; enable IHRC
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205 MOV a, #active_clock
206 MOV clkmd, a ; switch to IHRC
a43c9c44 207
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208 ;; .org 0xe8 ; comment out on 2nd iteration
209 ;; ; calibration placeholder:
210 ;; AND a, #'R'
211 ;; AND a, #'C'
212 ;; AND a, #1 ; IHRC
213 ;; AND a, #( calib_freq )
214 ;; AND a, #( calib_freq>>8 )
215 ;; AND a, #( calib_freq>>16 )
216 ;; AND a, #( calib_freq>>24 )
217 ;; AND a, #( calib_vdd )
218 ;; AND a, #( calib_vdd>>8 )
219 ;; AND a, #ihrcr
220 .org 0xfc
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221
222 ;stack setup:
223 MOV a, #stack_start
224 MOV sp, a
225
226 ; portA setup:
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227 MOV a, #0x50 ; data direction: PWM & debug output, rest input
228 MOV pac, a ; (conserves power, apparently)
229 MOV a, #(( 1<<4 ))
230 MOV padier, a ; disable pin wakeup, except on audio pin
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231 MOV pa, a ; PortA data = 0
232 MOV paph, a ; disable all pull-ups
233
234 ; timer2/pwm setup:
235 ; Since (unlike in the ATTiny4 version) the interrupt timer is not tied
236 ; to the PWM frequency, we can use a much faster clock for PWM. The
237 ; highest "carrier frequency" for the PCM samples we can generate is by
238 ; setting Timer2 to 6 bit, (IHRC/1)/1 mode, giving a frequency of
239 ; (4*4.096MHz)/2^6 = 256kHz.
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240 MOV pwm, a ; clear
241 MOV tm2b, a ; clear
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242 MOV a, #(( 2<<4 | 3<<2 | 1<<1 | 0<<0 ))
243 MOV tm2c, a ; timer2: IHRC, PA4, PWM, not inverted
244 MOV a, #(( 0<<7 | 1<<5 | 0<<0 ))
245 MOV tm2s, a ; 8bit, /4 prescaler, divide by (0+1)
f60af06d 246 ;XXX: increase pwm base frequency (/1) -> (4*4.096mhz)/(2^8) = 64khz
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247
248 ;timer16/ivr setup
249 ;mov a, #(( 0<<0 | 1<<3 | 4<<5 )) ; ovf@bit8 (512cy; §9.2.5), clk/4, ihrc
250 MOV a, #(( 1<<0 | 1<<3 | 4<<5 )) ; ovf@bit9 (???cy; §9.2.5), clk/4, ihrc
251 ;XXX: datasheet §5.10.1 says bit8 = 256cycles, 9.2.5 says bit8=512cy
252 ; note: ovf@bit9 causes 4khz isr => we need ovf@bit8.
253 MOV t16m, a
254 MOV a, #(1<<2) ; enable timer16 int, disable all others
255 MOV inten, a
256
257 ; misc setup:
258 SET1 eoscr, #0 ; disable bandgap and lvr
259 SET0 gpcc, #7 ; disable comparator
260
261 ; memory setup:
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262 CLEAR i0
263 CLEAR i1
264 CLEAR i2
265
a43c9c44 266 ;rom is not mmapped; must load notes into ram first
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267 MOV a, #0x84
268 MOV notes+0x0, a
269 MOV notes+0x5, a
270 MOV a, #0x9d
271 MOV notes+0x1, a
272 MOV notes+0x4, a
273 MOV a, #0xb0
274 MOV notes+0x2, a
275 MOV notes+0xA, a
276 MOV a, #0x69
277 MOV notes+0x3, a
278 MOV notes+0x6, a
279 MOV notes+0xB, a
280 MOV notes+0xE, a
281 MOV a, #0x58
282 MOV notes+0x7, a
283 MOV notes+0xF, a
284 MOV a, #0x75
285 MOV notes+0x8, a
286 MOV notes+0xD, a
287 MOV a, #0x8c
288 MOV notes+0x9, a
289 MOV notes+0xC, a
290
a43c9c44 291 ENGINT
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292
293loop:
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294 MOV a, i2
295 CEQSN a, #0x78 ; compare, skip next if equal
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296 ; Note: usually, this is the place where the MCU is put into some
297 ; sort of low power/sleep mode. But the Padauk's stopexe instruction
298 ; causes the ISR to a) run at greatly reduced frequency (100hz vs
299 ; 1khz for timer16@bit11; probably due to slow wakeup), b)
300 ; double-fire some (20-30%) of the time, c) jitter -50% to +10%. so
301 ; we don't sleep at all between samples (which is only a short time
302 ; anyways).
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303 GOTO loop
304
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305 ; at this point, i2==0x78, i.e. the music is finished.
306 ; => goto halt (fallthrough)
307halt:
308 DISGINT
309 CLEAR i2 ; clear halting signal
310
311 ; Note: disabling the timers isn't strictly necessary (as stopsys halts
312 ; all timers anyways), but I'm hoping it may reduce power consumption.
313 ; We're lucky that we only need to toggle a single bit to switch
314 ; between the required clock source and 'off' (0010xxxx->0000xxxx for
315 ; timer2, 100xxxxx->000xxxxx for timer16), so we can hack our way out
316 ; of loading an immediate each time.
317 SET0 tm2c, #5
318 SET0 t16m, #7
319
320 SET1 pa, #4 ; assert a high level on the audio pin for good measure
321 SET0 pac, #4 ; ... before setting it to input mode (optional)
322
323 ;switch to ilrc clock
324 MOV a, #sleep_clock
325 MOV clkmd, a
326 SET0 clkmd, #4 ; disable ihrc
327
328 STOPSYS
329 ; (at this point, we wait for an i/o-toggle wake up event to resume execution)
330
331 MOV a, #active_clock
332 MOV clkmd, a ; switch to IHRC again
333
334 SET1 pac, #4 ; restore output mode for audio pin
335
336 ;reenable timer16, timer2
337 SET1 tm2c, #5
338 SET1 t16m, #7
339
340 ENGINT
341 GOTO loop
342
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343interrupt:
344 PUSH af
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345 T1SN intrq, #2 ; if intrq.t16 is triggered, skip next
346 GOTO ivr_end
347
348 ;clear t16int:
349 SET0 intrq, #2
350
351 SET1 pa, #6 ; debug
352
54babda0 353 ; send pwm data to timer2:
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354 MOV a, pwm
355 ADD a, #4
356 MOV tm2b, a
ec2152ea 357
a43c9c44 358 ; generate new sample:
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359 MOV a, i2; "mov mem,mem"
360 MOV n, a; does not exist
361 SL n
362 SL n
363 MOV a, i1
364 SWAP a
365 AND a, #0xf
366 SR a
367 SR a
368 OR n, a
369
370 MOV a, n
371 CALL g
372 SWAP a
373 AND a, #0x1
374 MOV pwm, a
375
376 MOV a, i2
377 SL a
378 SL a
379 SL a
380 MOV tmp_1, a ; fresh tmp_1:
381 MOV a, i1
382 SWAP a
383 AND a, #0xf
384 SR a
385 OR a, tmp_1 ; tmp_1 done.
386 XOR a, n
387 CALL g
388 SR a
389 AND a, i2
390 SR a
391 AND a, #3
392 ADD pwm, a
393
394 MOV a, i2
395 MOV mod3hi, a
396 SR mod3hi
397 SR mod3hi
398 SR mod3hi
399 SWAP a
400 AND a, #0xf0
401 SL a
402 MOV mod3lo, a
403 MOV a, i1
404 SR a
405 SR a
406 SR a
407 OR mod3lo, a
408 CALL mod3
409 ADD a, n
410 CALL g
411 SR a
412 SR a
413 MOV tmp_1, a ; a saved in tmp_1; fresh a
414 MOV a, i2
415 ; shift-divide by six
416 ; note: i2 is max 0x78; so a will <= 20. (breaks vor values >=128)
417 SR a
418 ADD a, i2
419 SR a
420 SR a
421 ADD a, i2
422 SR a
423 SR a
424 ADD a, i2
425 SR a
426 SR a
427 SR a
428 ; end divide by six
429 AND a, tmp_1 ; a restored from tmp_1
430 AND a, #3
431 ADD pwm, a
432
433 MOV a, i2
434 MOV mod3hi, a
435 SR mod3hi
436 SR mod3hi
437 SWAP a
438 AND a, #0xf0
439 SL a
440 SL a
441 MOV mod3lo, a
442 MOV a, i1
443 SR a
444 SR a
445 OR mod3lo, a
446 CALL mod3
447 SUB a, n
448 SUB a, #8
449 NEG a
450 CALL g
451 SR a
452 MOV tmp_1, a ; a saved in tmp_1; fresh a
453 MOV a, i2
454 ; shift-divide by ten
455 ; note: i2 is max 0x78; so a will <= 12.
456 INC i2
457 SR a
458 ADD a, i2
459 SR a
460 SR a
461 SR a
462 ADD a, i2
463 SR a
464 ADD a, i2
465 SWAP a
466 DEC i2
467 ; end divide by ten
468 AND a, tmp_1 ; a restored from tmp_1
469 AND a, #3
29ec6906 470 ADD a, pwm
ec2152ea 471
ec2152ea 472 SWAP a
a43c9c44 473 MOV pwm, a
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474 ; next sample is now ready.
475
476 INC i0
477 ADDC i1
478 ADDC i2
479
f60af06d 480 SET0 pa, #6 ; debug
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481ivr_end:
482 POP af
ec2152ea 483 RETI
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