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Commit | Line | Data |
---|---|---|
1 | .area FUSE (ABS) | |
2 | .org 0x3ff*2 | |
3 | .word ( 0x0260 | 1<<0 | 5<<2 | 1<<7 | 3<<10 ) | |
4 | ; reserved_bits | security_off | lvr_1v8 | io_drv_norm | boot_fast | |
5 | ||
6 | .area OSEG (OVR,DATA) | |
7 | notes: .ds 16 ; 0x00 .. 0x0f | |
8 | i0: .ds 1 ; 0x10 | |
9 | i1: .ds 1 ; 0x11 | |
10 | i2: .ds 1 ; 0x12 | |
11 | n: .ds 1 ; 0x13 | |
12 | .even ; make next two bytes word-aligned | |
13 | zero: .ds 1 ; 0x14 | |
14 | tmp_1: .ds 1 ; 0x15 | |
15 | tmp_hi: .ds 1 ; 0x16 | |
16 | tmp_lo: .ds 1 ; 0x17 | |
17 | pwm: .ds 1 ; 0x18 | |
18 | ||
19 | .even ; SP must be aligned | |
20 | stack_start: .ds 1 | |
21 | .area SSEG | |
22 | stack: .ds 1 | |
23 | ||
24 | ; aliases for memory locations: | |
25 | notes_ix = tmp_1 | |
26 | t = tmp_1 | |
27 | mul2 = tmp_hi | |
28 | mul1 = tmp_lo | |
29 | mod3hi = tmp_hi | |
30 | mod3lo = tmp_lo | |
31 | ||
32 | ; io addresses | |
33 | clkmd = 0x03 | |
34 | inten = 0x04 | |
35 | intrq = 0x05 | |
36 | tm2c = 0x1C | |
37 | tm2b = 0x09 | |
38 | tm2s = 0x17 | |
39 | t16m = 0x06 | |
40 | eoscr = 0x0A | |
41 | padier = 0x0D | |
42 | pa = 0x10 | |
43 | pac = 0x11 | |
44 | paph = 0x12 | |
45 | misc = 0x1B | |
46 | gpcc = 0x1A | |
47 | ihrcr = 0x0B | |
48 | ||
49 | ; Calibration Parameters: | |
50 | ; Bitshift Variations calls for an 8kHz sample rate; with an interrupt every | |
51 | ; 512 cycles (the next power of two above the 495 cycles the program needs for | |
52 | ; execution), this gives us a clock speed of 512 * 8khz = 4.096MHz. The MCU | |
53 | ; will be powered by a 3V lithium coin cell. | |
54 | calib_freq = 4096000 ; Hz | |
55 | calib_vdd = 3000 ; mV | |
56 | ||
57 | ; Clock Parameters: | |
58 | ; during playback: IHRC/4, WDT off, keep ILRC on | |
59 | active_clock = (( 0<<5 | 1<<4 | 0<<3 | 1<<2 | 0<<1 | 0<<0 )) | |
60 | ; during deep-sleep: ILRC/1, WDT off | |
61 | sleep_clock = (( 7<<5 | 1<<4 | 0<<3 | 1<<2 | 0<<1 | 0<<0 )) | |
62 | ; for extra power saving, consider: 6<<5|0<<3 for ilrc/6, 2<<5|1<<3 for ilrc/16 | |
63 | ||
64 | ; cycle count (worst-case) | |
65 | ; mod3: 28 | |
66 | ; g: 81 | |
67 | ; sample: 115 + 4*g + 2*mod3 = 495 | |
68 | ; isr overhead: 12 | |
69 | ; TOTAL: sample + overhead = 507 | |
70 | ||
71 | ; portA.4: audio out | |
72 | ; portA.6: debug pin | |
73 | ||
74 | ||
75 | .area CSEG (CODE,ABS) | |
76 | .org 0x0000 | |
77 | GOTO init | |
78 | ||
79 | .org 0x0020 | |
80 | GOTO interrupt | |
81 | ||
82 | mod3: | |
83 | MOV a, mod3hi | |
84 | ADD mod3lo, a ; mod3lo = hi+lo | |
85 | MOV a, #0 | |
86 | ADDC a ; mod3hi, 1bit | |
87 | SWAP a | |
88 | MOV mod3hi, a | |
89 | ||
90 | MOV a, mod3lo | |
91 | SWAP a | |
92 | AND a, #0xf ; (mod3lo>>4) | |
93 | XCH mod3lo ; a=mod3lo, mod3lo=mod3lo>>4 | |
94 | AND a, #0xF ; a=mod3lo&0xf, mod3lo=mod3lo>>4 | |
95 | ADD a, mod3lo ; (mod3lo & 0xF) | |
96 | ADD a, mod3hi | |
97 | MOV mod3lo, a | |
98 | ||
99 | AND a, #0x3 ; a = (mod3lo & 0x3) | |
100 | SR mod3lo | |
101 | SR mod3lo ; (mod3lo >> 2) | |
102 | ADD a, mod3lo | |
103 | MOV mod3lo, a | |
104 | ||
105 | AND a, #0x3 ; a = (mod3lo & 0x3) | |
106 | SR mod3lo | |
107 | SR mod3lo ; (mod3lo >> 2) | |
108 | ADD a, mod3lo | |
109 | ||
110 | SUB a, #3 | |
111 | T0SN f, c | |
112 | ADD a, #3 | |
113 | RET | |
114 | ||
115 | g: | |
116 | ; notes_ix_hi = always 0 | |
117 | AND a, #0x7 | |
118 | MOV notes_ix, a | |
119 | ; test i2 & 3: | |
120 | MOV a, i2 | |
121 | AND a, #3 | |
122 | T0SN f, z | |
123 | SET1 notes_ix, #3 | |
124 | IDXM a, notes_ix | |
125 | ||
126 | MOV t, a | |
127 | CLEAR mul2 | |
128 | CLEAR mul1 | |
129 | ; note: LSB of result (mul0) is not needed for our purposes | |
130 | ;;1/8: | |
131 | SR t | |
132 | T1SN f, c | |
133 | GOTO skip1 | |
134 | MOV a, i0 | |
135 | ADD mul1, a | |
136 | MOV a, i1 | |
137 | ADDC mul2, a | |
138 | skip1: SR mul2 | |
139 | SRC mul1 | |
140 | ;;2/8: | |
141 | SR t | |
142 | skip2: SR mul2 | |
143 | SRC mul1 | |
144 | ;;3/8: | |
145 | SR t | |
146 | T1SN f, c | |
147 | GOTO skip3 | |
148 | MOV a, i0 | |
149 | ADD mul1, a | |
150 | MOV a, i1 | |
151 | ADDC mul2, a | |
152 | skip3: SR mul2 | |
153 | SRC mul1 | |
154 | ;;4/8: | |
155 | SR t | |
156 | T1SN f, c | |
157 | GOTO skip4 | |
158 | MOV a, i0 | |
159 | ADD mul1, a | |
160 | MOV a, i1 | |
161 | ADDC mul2, a | |
162 | skip4: SR mul2 | |
163 | SRC mul1 | |
164 | ;;5/8: | |
165 | SR t | |
166 | T1SN f, c | |
167 | GOTO skip5 | |
168 | MOV a, i0 | |
169 | ADD mul1, a | |
170 | MOV a, i1 | |
171 | ADDC mul2, a | |
172 | skip5: SR mul2 | |
173 | SRC mul1 | |
174 | ;;6/8: | |
175 | SR t | |
176 | T1SN f, c | |
177 | GOTO skip6 | |
178 | MOV a, i0 | |
179 | ADD mul1, a | |
180 | skip6: | |
181 | SRC mul1 | |
182 | ;;7/8: | |
183 | SR t | |
184 | T1SN f, c | |
185 | GOTO skip7 | |
186 | MOV a, i0 | |
187 | ADD mul1, a | |
188 | skip7: | |
189 | SRC mul1 | |
190 | ;;8/8: | |
191 | SR t | |
192 | T1SN f, c | |
193 | GOTO skip8 | |
194 | MOV a, i0 | |
195 | ADD mul1, a | |
196 | skip8: | |
197 | SRC mul1 | |
198 | ||
199 | MOV a, mul1 | |
200 | RET | |
201 | ||
202 | init: | |
203 | ; clock setup: | |
204 | SET1 clkmd, #4 ; enable IHRC | |
205 | MOV a, #active_clock | |
206 | MOV clkmd, a ; switch to IHRC | |
207 | ||
208 | ;; .org 0xe8 ; comment out on 2nd iteration | |
209 | ;; ; calibration placeholder: | |
210 | ;; AND a, #'R' | |
211 | ;; AND a, #'C' | |
212 | ;; AND a, #1 ; IHRC | |
213 | ;; AND a, #( calib_freq ) | |
214 | ;; AND a, #( calib_freq>>8 ) | |
215 | ;; AND a, #( calib_freq>>16 ) | |
216 | ;; AND a, #( calib_freq>>24 ) | |
217 | ;; AND a, #( calib_vdd ) | |
218 | ;; AND a, #( calib_vdd>>8 ) | |
219 | ;; AND a, #ihrcr | |
220 | .org 0xfc | |
221 | ||
222 | ;stack setup: | |
223 | MOV a, #stack_start | |
224 | MOV sp, a | |
225 | ||
226 | ; portA setup: | |
227 | MOV a, #0x50 ; data direction: PWM & debug output, rest input | |
228 | MOV pac, a ; (conserves power, apparently) | |
229 | MOV a, #(( 1<<4 )) | |
230 | MOV padier, a ; disable pin wakeup, except on audio pin | |
231 | MOV pa, a ; PortA data = 0 | |
232 | MOV paph, a ; disable all pull-ups | |
233 | ||
234 | ; timer2/pwm setup: | |
235 | ; Since (unlike in the ATTiny4 version) the interrupt timer is not tied | |
236 | ; to the PWM frequency, we can use a much faster clock for PWM. The | |
237 | ; highest "carrier frequency" for the PCM samples we can generate is by | |
238 | ; setting Timer2 to 6 bit, (IHRC/1)/1 mode, giving a frequency of | |
239 | ; (4*4.096MHz)/2^6 = 256kHz. | |
240 | MOV pwm, a ; clear | |
241 | MOV tm2b, a ; clear | |
242 | MOV a, #(( 2<<4 | 3<<2 | 1<<1 | 0<<0 )) | |
243 | MOV tm2c, a ; timer2: IHRC, PA4, PWM, not inverted | |
244 | MOV a, #(( 0<<7 | 1<<5 | 0<<0 )) | |
245 | MOV tm2s, a ; 8bit, /4 prescaler, divide by (0+1) | |
246 | ;XXX: increase pwm base frequency (/1) -> (4*4.096mhz)/(2^8) = 64khz | |
247 | ||
248 | ;timer16/ivr setup | |
249 | MOV a, #(( 0<<0 | 1<<3 | 4<<5 )) ; ovf@bit8 (512cy; ยง9.2.5), clk/4, ihrc | |
250 | MOV t16m, a | |
251 | MOV a, #(1<<2) ; enable timer16 int, disable all others | |
252 | MOV inten, a | |
253 | ||
254 | ; misc setup: | |
255 | SET1 eoscr, #0 ; disable bandgap and lvr | |
256 | SET0 gpcc, #7 ; disable comparator | |
257 | ||
258 | ; memory setup: | |
259 | CLEAR i0 | |
260 | CLEAR i1 | |
261 | CLEAR i2 | |
262 | ||
263 | ;rom is not mmapped; must load notes into ram first | |
264 | MOV a, #0x84 | |
265 | MOV notes+0x0, a | |
266 | MOV notes+0x5, a | |
267 | MOV a, #0x9d | |
268 | MOV notes+0x1, a | |
269 | MOV notes+0x4, a | |
270 | MOV a, #0xb0 | |
271 | MOV notes+0x2, a | |
272 | MOV notes+0xA, a | |
273 | MOV a, #0x69 | |
274 | MOV notes+0x3, a | |
275 | MOV notes+0x6, a | |
276 | MOV notes+0xB, a | |
277 | MOV notes+0xE, a | |
278 | MOV a, #0x58 | |
279 | MOV notes+0x7, a | |
280 | MOV notes+0xF, a | |
281 | MOV a, #0x75 | |
282 | MOV notes+0x8, a | |
283 | MOV notes+0xD, a | |
284 | MOV a, #0x8c | |
285 | MOV notes+0x9, a | |
286 | MOV notes+0xC, a | |
287 | ||
288 | ENGINT | |
289 | ||
290 | loop: | |
291 | MOV a, i2 | |
292 | CEQSN a, #0x78 ; compare, skip next if equal | |
293 | ; Note: usually, this is the place where the MCU is put into some | |
294 | ; sort of low power/sleep mode. But the Padauk's stopexe instruction | |
295 | ; causes the ISR to a) run at greatly reduced frequency (100hz vs | |
296 | ; 1khz for timer16@bit11; probably due to slow wakeup), b) | |
297 | ; double-fire some (20-30%) of the time, c) jitter -50% to +10%. so | |
298 | ; we don't sleep at all between samples (which is only a short time | |
299 | ; anyways). | |
300 | GOTO loop | |
301 | ||
302 | ; at this point, i2==0x78, i.e. the music is finished. | |
303 | ; => goto halt (fallthrough) | |
304 | halt: | |
305 | DISGINT | |
306 | CLEAR i2 ; clear halting signal | |
307 | ||
308 | ; Note: disabling the timers isn't strictly necessary (as stopsys halts | |
309 | ; all timers anyways), but I'm hoping it may reduce power consumption. | |
310 | ; We're lucky that we only need to toggle a single bit to switch | |
311 | ; between the required clock source and 'off' (0010xxxx->0000xxxx for | |
312 | ; timer2, 100xxxxx->000xxxxx for timer16), so we can hack our way out | |
313 | ; of loading an immediate each time. | |
314 | SET0 tm2c, #5 | |
315 | SET0 t16m, #7 | |
316 | ||
317 | SET1 pa, #4 ; assert a high level on the audio pin for good measure | |
318 | SET0 pac, #4 ; ... before setting it to input mode (optional) | |
319 | ||
320 | ;switch to ilrc clock | |
321 | MOV a, #sleep_clock | |
322 | MOV clkmd, a | |
323 | SET0 clkmd, #4 ; disable ihrc | |
324 | ||
325 | STOPSYS | |
326 | ; (at this point, we wait for an i/o-toggle wake up event to resume execution) | |
327 | ||
328 | MOV a, #active_clock | |
329 | MOV clkmd, a ; switch to IHRC again | |
330 | ||
331 | SET1 pac, #4 ; restore output mode for audio pin | |
332 | ||
333 | ;reenable timer16, timer2 | |
334 | SET1 tm2c, #5 | |
335 | SET1 t16m, #7 | |
336 | ||
337 | ENGINT | |
338 | GOTO loop | |
339 | ||
340 | interrupt: | |
341 | PUSH af | |
342 | T1SN intrq, #2 ; if intrq.t16 is triggered, skip next | |
343 | GOTO ivr_end | |
344 | ||
345 | ;clear t16int: | |
346 | SET0 intrq, #2 | |
347 | ||
348 | SET1 pa, #6 ; debug | |
349 | ||
350 | ; send pwm data to timer2: | |
351 | MOV a, pwm | |
352 | ADD a, #4 | |
353 | MOV tm2b, a | |
354 | ||
355 | ; generate new sample: | |
356 | MOV a, i2; "mov mem,mem" | |
357 | MOV n, a; does not exist | |
358 | SL n | |
359 | SL n | |
360 | MOV a, i1 | |
361 | SWAP a | |
362 | AND a, #0xf | |
363 | SR a | |
364 | SR a | |
365 | OR n, a | |
366 | ||
367 | MOV a, n | |
368 | CALL g | |
369 | SWAP a | |
370 | AND a, #0x1 | |
371 | MOV pwm, a | |
372 | ||
373 | MOV a, i2 | |
374 | SL a | |
375 | SL a | |
376 | SL a | |
377 | MOV tmp_1, a ; fresh tmp_1: | |
378 | MOV a, i1 | |
379 | SWAP a | |
380 | AND a, #0xf | |
381 | SR a | |
382 | OR a, tmp_1 ; tmp_1 done. | |
383 | XOR a, n | |
384 | CALL g | |
385 | SR a | |
386 | AND a, i2 | |
387 | SR a | |
388 | AND a, #3 | |
389 | ADD pwm, a | |
390 | ||
391 | MOV a, i2 | |
392 | MOV mod3hi, a | |
393 | SR mod3hi | |
394 | SR mod3hi | |
395 | SR mod3hi | |
396 | SWAP a | |
397 | AND a, #0xf0 | |
398 | SL a | |
399 | MOV mod3lo, a | |
400 | MOV a, i1 | |
401 | SR a | |
402 | SR a | |
403 | SR a | |
404 | OR mod3lo, a | |
405 | CALL mod3 | |
406 | ADD a, n | |
407 | CALL g | |
408 | SR a | |
409 | SR a | |
410 | MOV tmp_1, a ; a saved in tmp_1; fresh a | |
411 | MOV a, i2 | |
412 | ; shift-divide by six | |
413 | ; note: i2 is max 0x78; so a will <= 20. (breaks vor values >=128) | |
414 | SR a | |
415 | ADD a, i2 | |
416 | SR a | |
417 | SR a | |
418 | ADD a, i2 | |
419 | SR a | |
420 | SR a | |
421 | ADD a, i2 | |
422 | SR a | |
423 | SR a | |
424 | SR a | |
425 | ; end divide by six | |
426 | AND a, tmp_1 ; a restored from tmp_1 | |
427 | AND a, #3 | |
428 | ADD pwm, a | |
429 | ||
430 | MOV a, i2 | |
431 | MOV mod3hi, a | |
432 | SR mod3hi | |
433 | SR mod3hi | |
434 | SWAP a | |
435 | AND a, #0xf0 | |
436 | SL a | |
437 | SL a | |
438 | MOV mod3lo, a | |
439 | MOV a, i1 | |
440 | SR a | |
441 | SR a | |
442 | OR mod3lo, a | |
443 | CALL mod3 | |
444 | SUB a, n | |
445 | SUB a, #8 | |
446 | NEG a | |
447 | CALL g | |
448 | SR a | |
449 | MOV tmp_1, a ; a saved in tmp_1; fresh a | |
450 | MOV a, i2 | |
451 | ; shift-divide by ten | |
452 | ; note: i2 is max 0x78; so a will <= 12. | |
453 | INC i2 | |
454 | SR a | |
455 | ADD a, i2 | |
456 | SR a | |
457 | SR a | |
458 | SR a | |
459 | ADD a, i2 | |
460 | SR a | |
461 | ADD a, i2 | |
462 | SWAP a | |
463 | DEC i2 | |
464 | ; end divide by ten | |
465 | AND a, tmp_1 ; a restored from tmp_1 | |
466 | AND a, #3 | |
467 | ADD a, pwm | |
468 | ||
469 | SWAP a | |
470 | MOV pwm, a | |
471 | ; next sample is now ready. | |
472 | ||
473 | INC i0 | |
474 | ADDC i1 | |
475 | ADDC i2 | |
476 | ||
477 | SET0 pa, #6 ; debug | |
478 | ivr_end: | |
479 | POP af | |
480 | RETI |