make timer16 overflow every 512 cycles

[Chiptunes-pms150c.git] / bsv.asm

diff --git a/bsv.asm b/bsv.asm
index e83e3a4cd32f32ce4043cdb1859683534424daef..f31ee13cac06824bc715b6acf2562a8767f0e4ac 100644 (file)
--- a/bsv.asm
+++ b/bsv.asm
@@ -50,7 +50,7 @@ ihrcr = 0x0B
 ; Bitshift Variations calls for an 8kHz sample rate; with an interrupt every
 ; 512 cycles (the next power of two above the 495 cycles the program needs for
 ; execution), this gives us a clock speed of 512 * 8khz = 4.096MHz. The MCU
-; will be powered by a 3V lithium coin cell. (+10-15ish cycles ivr overhead)
+; will be powered by a 3V lithium coin cell.
 calib_freq = 4096000 ; Hz
 calib_vdd  = 3000 ; mV
 
@@ -65,6 +65,8 @@ sleep_clock = (( 7<<5 | 1<<4 | 0<<3 | 1<<2 | 0<<1 | 0<<0 ))
 ; mod3:    28
 ; g:       81
 ; sample: 115 + 4*g + 2*mod3 = 495
+; isr overhead: 12
+; TOTAL: sample + overhead = 507
 
 ; portA.4: audio out
 ; portA.6: debug pin
@@ -203,19 +205,19 @@ init:
        MOV     a, #active_clock
        MOV     clkmd, a        ; switch to IHRC
 
-       ;; .org 0x46 ; comment out on 2nd iteration
-       ; calibration placeholder:
-       AND     a, #'R'
-       AND     a, #'C'
-       AND     a, #1 ; IHRC
-       AND     a, #( calib_freq )
-       AND     a, #( calib_freq>>8 )
-       AND     a, #( calib_freq>>16 )
-       AND     a, #( calib_freq>>24 )
-       AND     a, #( calib_vdd )
-       AND     a, #( calib_vdd>>8 )
-       AND     a, #ihrcr
-       ;; .org 0x5a
+       ;; .org 0xe8 ; comment out on 2nd iteration
+       ;; ; calibration placeholder:
+       ;; AND  a, #'R'
+       ;; AND  a, #'C'
+       ;; AND  a, #1 ; IHRC
+       ;; AND  a, #( calib_freq )
+       ;; AND  a, #( calib_freq>>8 )
+       ;; AND  a, #( calib_freq>>16 )
+       ;; AND  a, #( calib_freq>>24 )
+       ;; AND  a, #( calib_vdd )
+       ;; AND  a, #( calib_vdd>>8 )
+       ;; AND  a, #ihrcr
+       .org 0xfc
 
        ;stack setup:
        MOV     a, #stack_start
@@ -241,12 +243,10 @@ init:
        MOV     tm2c, a         ; timer2: IHRC, PA4, PWM, not inverted
        MOV     a, #(( 0<<7 | 1<<5 | 0<<0 ))
        MOV     tm2s, a         ; 8bit, /4 prescaler, divide by (0+1)
+       ;XXX: increase pwm base frequency (/1) -> (4*4.096mhz)/(2^8) = 64khz
 
        ;timer16/ivr setup
-       ;mov    a, #(( 0<<0 | 1<<3 | 4<<5 ))    ; ovf@bit8 (512cy; §9.2.5), clk/4, ihrc
-       MOV     a, #(( 1<<0 | 1<<3 | 4<<5 ))    ; ovf@bit9 (???cy; §9.2.5), clk/4, ihrc
-       ;XXX: datasheet §5.10.1 says bit8 = 256cycles, 9.2.5 says bit8=512cy
-       ; note: ovf@bit9 causes 4khz isr => we need ovf@bit8.
+       MOV     a, #(( 0<<0 | 1<<3 | 4<<5 ))    ; ovf@bit8 (512cy; §9.2.5), clk/4, ihrc
        MOV     t16m, a
        MOV     a, #(1<<2)              ; enable timer16 int, disable all others
        MOV     inten, a
@@ -474,7 +474,7 @@ interrupt:
        ADDC    i1
        ADDC    i2
 
-       SET1    pa, #6          ; debug
+       SET0    pa, #6          ; debug
 ivr_end:
        POP     af
        RETI