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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
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5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
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10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
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14u8 x;
15u8 t;
16u8 o;
49137fbf 17u8 _;
e98ab46f 18#define Mh o //mod3 vars
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19#define Ml t // -"-
20void mod3(void) { //avail: t, o _
e98ab46f 21//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
5b1c6cc5 22 #define tmp _
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23 ADD (Ml, Mh)
24 CLR (Mh)
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25 ADC (Mh, zero, carry) //Mh only holds the carry bit
26 MOV (tmp, Ml)
27 SWAP (tmp)
28 ANDI (tmp, 0x0f)
29 SWAP (Mh)
30 OR (tmp, Mh)
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31 ANDI (Ml, 0x0f)
32 ADD (Ml, tmp) //discard tmp
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33 Ml = (Ml >> 2) + (Ml & 0x3);
34 Ml = (Ml >> 2) + (Ml & 0x3);
35 if (Ml > 2) Ml = Ml - 3;
5b1c6cc5 36 #undef tmp
e98ab46f 37}
965274e2 38void g(void) {
46a8d83c 39 // g(i, x, t, o) -> t
49137fbf 40 #define tmp _
0f219114 41 ANDI (t, 0x07)
32632e61 42 MOV (tmp, i2)
63363195 43 ANDI (tmp, 3)
09cf3949 44 TST (tmp)
49137fbf 45 #undef tmp
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46 BREQ (skip)
47 SUBI (t, -8)
48 skip:
c616f0c2 49 t = data[t];
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50 /*MOV X_hi==_, data_hi
51 MOV X_lo==t, data_lo
52 ADD X_lo, t
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53 ADC X_hi, zero
54 LD t, X */
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55 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
56 t >>= o; //NOTE: o == {1, 2, 4}
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57 AND (t, x)
58 ANDI (t, 3)
46a8d83c 59 RET
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60};
61
62int main(void) {
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63 u8 n;
64 u8 s;
ab6fe4c2 65 u8 acc;
89f35588 66 //TODO: clear all vars/registers
5dd8b8ff 67 for (;;) {
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68 MOV (n, i2)
69 LSL (n)
70 LSL (n)
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71 #define tmp acc
72 MOV (tmp, i1)
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73 SWAP (tmp)
74 ANDI (tmp, 0x0f)
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75 LSR (tmp)
76 LSR (tmp)
128ff01a 77 OR (n, tmp)
bc7680e3 78 #undef tmp
df192822 79 MOV (s, i3)
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80 ROR (s)
81 ROR (s)
82 ANDI (s, 0x80)
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83 #define tmp acc
84 MOV (tmp, i2)
85 LSR (tmp)
e389879f 86 OR (s, tmp)
df192822 87 #undef tmp
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88
89 //voice 1:
90 LDI (x, 1)
91 MOV (t, n)
9401049b 92 LDI (o, 4)
965274e2 93 RCALL g();
46a8d83c 94 MOV (acc, t)
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95
96 //voice 2:
97 MOV (x, s)
1b023e92 98 #define tmp o
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99 MOV (tmp, i2)
100 LSL (tmp)
101 LSL (tmp)
102 LSL (tmp)
103 MOV (t, i1)
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104 SWAP (t)
105 ANDI (t, 0xf)
106 LSR (t)
94c4920f 107 OR (t, tmp)
1b023e92 108 #undef tmp
23872091 109 EOR (t, n)
9401049b 110 LDI (o, 2)
965274e2 111 RCALL g();
46a8d83c 112 ADD (acc, t)
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113
114 //voice 3:
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115 MOV (x, s)
116 INC (x)
17c5b4e9 117 #define tmp o
a7a7abba 118 MOV (tmp, x)
f84bcb7f 119 LSR (tmp)
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120 LSR (tmp)
121 ADD (tmp, x)
122 ROR (tmp)
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123 LSR (tmp)
124 ADD (tmp, x)
125 ROR (tmp)
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126 LSR (tmp)
127 ADD (tmp, x)
128 ROR (tmp)
546b5bab 129 LSR (tmp)
2c94c801 130 MOV (x, tmp)
17c5b4e9 131 #undef tmp
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132 Ml = i2<<5 | i1>>3;
133 Mh = i3<<5 | i2>>3;
dbf91c38 134 RCALL mod3();
18570947 135 ADD (t, n)
9401049b 136 LDI (o, 2)
965274e2 137 RCALL g();
46a8d83c 138 ADD (acc, t)
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139
140 //voice 4:
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141 MOV (x, s)
142 INC (x)
143 #define tmp o
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144 MOV (tmp, x)
145 LSR (tmp)
146 ADD (tmp, x)
147 ROR (tmp)
86f35aa4 148 LSR (tmp)
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149 LSR (tmp)
150 ADD (tmp, x)
151 ROR (tmp)
152 ADD (tmp, x)
153 ROR (tmp)
86f35aa4 154 LSR (tmp)
86f35aa4 155 LSR (tmp)
c2693411 156 MOV (x, tmp)
6bc3ca83 157 #undef tmp
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158 Ml = i2<<6 | i1>>2;
159 Mh = i3<<6 | i2>>2;
dbf91c38 160 RCALL mod3();
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161 SUB (t, n)
162 NEG (t)
902cfdea 163 SUBI (t, -8)
9401049b 164 LDI (o, 1)
965274e2 165 RCALL g();
46a8d83c 166 ADD (acc, t)
bfce2f8c 167
95fa231f 168 putchar(acc<<4); //TODO
89f35588 169 SUBI (i0, -1)
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170 ADC (i1, zero, !i0)
171 ADC (i2, zero, !i0&&!i1)
172 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 173 }
61fab018 174}
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