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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
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10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
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14u8 n;
15u8 s;
16u8 acc;
17u8 t;
18u8 x;
19u8 _;
37bf20ea 20#define Mh x //mod3 vars
dbf91c38 21#define Ml t // -"-
e98ab46f 22//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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23void mod3(void) {
24 // mod3(Mh.Ml) -> t
25 #define tmp _
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26 ADD (Ml, Mh)
27 CLR (Mh)
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28 ADC (Mh, zero, carry) //Mh only holds the carry bit
29 MOV (tmp, Ml)
30 SWAP (tmp)
31 ANDI (tmp, 0x0f)
32 SWAP (Mh)
33 OR (tmp, Mh)
0e3d0279 34 ANDI (Ml, 0x0f)
2a69999d 35 ADD (Ml, tmp)
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36 MOV (tmp, Ml)
37 LSR (tmp)
38 LSR (tmp)
6c72d3c1 39 ANDI (Ml, 0x03)
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40 ADD (Ml, tmp)
41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
44 ANDI (Ml, 0x03)
45 ADD (Ml, tmp)
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46 CPI (Ml, 3)
47 BRPL (skip)
197a5418 48 SUBI (Ml, 3)
c3639d5b 49 skip:;
4283632d 50 RET
8d8c00e4 51 #undef tmp
e98ab46f 52}
965274e2 53void g(void) {
362b33c9 54 // g(i, t) -> t
eafeaf93 55 // tempvars: `x` and `_`
49137fbf 56 #define tmp _
0f219114 57 ANDI (t, 0x07)
32632e61 58 MOV (tmp, i2)
63363195 59 ANDI (tmp, 3)
09cf3949 60 TST (tmp)
49137fbf 61 #undef tmp
09cf3949
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62 BREQ (skip)
63 SUBI (t, -8)
64 skip:
c616f0c2 65 t = data[t];
8ee3310e 66 /*MOV X_hi==x, data_hi
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67 MOV X_lo==t, data_lo
68 ADD X_lo, t
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69 ADC X_hi, zero
70 LD t, X */
e5715654 71 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
d5b74a12 72 RET //TODO: replace CALL/RET with IJMP?
61fab018
TG
73};
74
75int main(void) {
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76 CLR (zero)
77 CLR (i0)
78 CLR (i1)
79 CLR (i2)
80 CLR (i3)
5dd8b8ff 81 for (;;) {
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82 MOV (n, i2)
83 LSL (n)
84 LSL (n)
8ee3310e 85 #define tmp _
bc7680e3 86 MOV (tmp, i1)
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87 SWAP (tmp)
88 ANDI (tmp, 0x0f)
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89 LSR (tmp)
90 LSR (tmp)
128ff01a 91 OR (n, tmp)
bc7680e3 92 #undef tmp
df192822 93 MOV (s, i3)
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94 ROR (s)
95 ROR (s)
96 ANDI (s, 0x80)
8ee3310e 97 #define tmp _
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98 MOV (tmp, i2)
99 LSR (tmp)
e389879f 100 OR (s, tmp)
df192822 101 #undef tmp
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102
103 //voice 1:
3b86ca43 104 MOV (t, n)
965274e2 105 RCALL g();
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106 SWAP (t)
107 ANDI (t, 0x0f)
f28def6a 108 ANDI (t, 1)
46a8d83c 109 MOV (acc, t)
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110
111 //voice 2:
37bf20ea 112 #define tmp _
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113 MOV (tmp, i2)
114 LSL (tmp)
115 LSL (tmp)
116 LSL (tmp)
117 MOV (t, i1)
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118 SWAP (t)
119 ANDI (t, 0xf)
120 LSR (t)
94c4920f 121 OR (t, tmp)
1b023e92 122 #undef tmp
23872091 123 EOR (t, n)
965274e2 124 RCALL g();
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125 LSR (t)
126 LSR (t)
127 ANDI (t, 3)
f28def6a 128 AND (t, s)
46a8d83c 129 ADD (acc, t)
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130
131 //voice 3:
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132 MOV (Ml, i2)
133 SWAP (Ml)
134 ANDI (Ml, 0xf0)
135 LSL (Ml)
8ee3310e 136 #define tmp _
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137 MOV (tmp, i1)
138 LSR (tmp)
139 LSR (tmp)
140 LSR (tmp)
141 OR (Ml, tmp)
142 #undef tmp
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143 MOV (Mh, i3)
144 SWAP (Mh)
145 ANDI (Mh, 0xf0)
146 LSL (Mh)
147 #define tmp _
148 MOV (tmp, i2)
149 LSR (tmp)
150 LSR (tmp)
151 LSR (tmp)
152 OR (Mh, tmp)
153 #undef tmp
dbf91c38 154 RCALL mod3();
18570947 155 ADD (t, n)
965274e2 156 RCALL g();
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157 LSR (t)
158 LSR (t)
159 ANDI (t, 3)
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160 MOV (x, s)
161 INC (x)
37bf20ea 162 #define tmp _
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163 MOV (tmp, x)
164 LSR (tmp)
165 LSR (tmp)
166 ADD (tmp, x)
167 ROR (tmp)
168 LSR (tmp)
169 ADD (tmp, x)
170 ROR (tmp)
171 LSR (tmp)
172 ADD (tmp, x)
173 ROR (tmp)
174 LSR (tmp)
175 MOV (x, tmp)
176 #undef tmp
5d9a2389 177 AND (t, x)
46a8d83c 178 ADD (acc, t)
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179
180 //voice 4:
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181 MOV (Ml, i2)
182 SWAP (Ml)
183 ANDI (Ml, 0xf0)
184 LSL (Ml)
185 LSL (Ml)
8ee3310e 186 #define tmp _
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187 MOV (tmp, i1)
188 LSR (tmp)
189 LSR (tmp)
190 OR (Ml, tmp)
191 #undef tmp
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192 MOV (Mh, i3)
193 SWAP (Mh)
194 ANDI (Mh, 0xf0)
195 LSL (Mh)
196 LSL (Mh)
197 #define tmp _
198 MOV (tmp, i2)
199 LSR (tmp)
200 LSR (tmp)
201 OR (Mh, tmp)
202 #undef tmp
dbf91c38 203 RCALL mod3();
e4f7baf0
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204 SUB (t, n)
205 NEG (t)
902cfdea 206 SUBI (t, -8)
965274e2 207 RCALL g();
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208 LSR (t)
209 ANDI (t, 3)
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210 MOV (x, s)
211 INC (x)
37bf20ea 212 #define tmp _
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213 MOV (tmp, x)
214 LSR (tmp)
215 ADD (tmp, x)
216 ROR (tmp)
217 LSR (tmp)
218 LSR (tmp)
219 ADD (tmp, x)
220 ROR (tmp)
221 ADD (tmp, x)
222 ROR (tmp)
223 LSR (tmp)
224 LSR (tmp)
225 MOV (x, tmp)
226 #undef tmp
5d9a2389 227 AND (t, x)
46a8d83c 228 ADD (acc, t)
bfce2f8c 229
95fa231f 230 putchar(acc<<4); //TODO
89f35588 231 SUBI (i0, -1)
95fa231f
TG
232 ADC (i1, zero, !i0)
233 ADC (i2, zero, !i0&&!i1)
234 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 235 }
61fab018 236}
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