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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
61592bdd
TG
9u8 zero; //r16
10u8 acc; //r17
11u8 i0; //r18
12u8 i1; //r19
13u8 i2; //r20
14u8 i3; //r21
15u8 n; //r22
16u8 s; //r23
17u8 _; //r24
18 //r25
19u8 t;/*==Ml*/ //r26 (Xlo)
20u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23/*fakestack_l*/ //r30 (Zlo)
24/*fakestack_h*/ //r31 (Zhi)
37bf20ea 25#define Mh x //mod3 vars
dbf91c38 26#define Ml t // -"-
e98ab46f 27//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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28void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
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31 ADD (Ml, Mh)
32 CLR (Mh)
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33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
0e3d0279 39 ANDI (Ml, 0x0f)
2a69999d 40 ADD (Ml, tmp)
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41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
6c72d3c1 44 ANDI (Ml, 0x03)
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45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
c3639d5b
TG
51 CPI (Ml, 3)
52 BRPL (skip)
197a5418 53 SUBI (Ml, 3)
c3639d5b 54 skip:;
4283632d 55 RET
8d8c00e4 56 #undef tmp
e98ab46f 57}
965274e2 58void g(void) {
362b33c9 59 // g(i, t) -> t
eafeaf93 60 // tempvars: `x` and `_`
49137fbf 61 #define tmp _
0f219114 62 ANDI (t, 0x07)
32632e61 63 MOV (tmp, i2)
63363195 64 ANDI (tmp, 3)
09cf3949 65 TST (tmp)
49137fbf 66 #undef tmp
09cf3949
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67 BREQ (skip)
68 SUBI (t, -8)
69 skip:
c616f0c2 70 t = data[t];
8ee3310e 71 /*MOV X_hi==x, data_hi
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72 MOV X_lo==t, data_lo
73 ADD X_lo, t
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74 ADC X_hi, zero
75 LD t, X */
5700437a
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76 #define a1 x
77 #define a2 _
d397f897 78 #define a0 t
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79 CLR (a2)
80 CLR (a1)
d397f897 81 for (u8 loop = 0; loop < 8; loop++) { //Note: t&2 always zero
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82 SBRS (t, 0)
83 goto skip2;
d397f897 84 if (t & 1) {
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85 ADD (a1, i0)
86 ADC (a2, i1, carry)
d397f897 87 }
7b96a97d 88 skip2:
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89 LSR (a2)
90 ROR (a1)
91 ROR (t)
d397f897 92 }
27ca59e7 93 MOV (t, a1) //can't return x or _ as a1, both needed later besides t
5700437a 94 #undef a0
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95 #undef a1
96 #undef a2
d397f897 97
d5b74a12 98 RET //TODO: replace CALL/RET with IJMP?
61fab018
TG
99};
100
101int main(void) {
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102 CLR (zero)
103 CLR (i0)
104 CLR (i1)
105 CLR (i2)
106 CLR (i3)
5dd8b8ff 107 for (;;) {
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108 MOV (n, i2)
109 LSL (n)
110 LSL (n)
8ee3310e 111 #define tmp _
bc7680e3 112 MOV (tmp, i1)
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113 SWAP (tmp)
114 ANDI (tmp, 0x0f)
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115 LSR (tmp)
116 LSR (tmp)
128ff01a 117 OR (n, tmp)
bc7680e3 118 #undef tmp
df192822 119 MOV (s, i3)
2bbe001f 120 LSR (s)
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121 ROR (s)
122 ANDI (s, 0x80)
8ee3310e 123 #define tmp _
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124 MOV (tmp, i2)
125 LSR (tmp)
e389879f 126 OR (s, tmp)
df192822 127 #undef tmp
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128
129 //voice 1:
3b86ca43 130 MOV (t, n)
965274e2 131 RCALL g();
c09a6ed8 132 SWAP (t)
9e62fea4 133 ANDI (t, 1)
46a8d83c 134 MOV (acc, t)
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135
136 //voice 2:
37bf20ea 137 #define tmp _
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138 MOV (tmp, i2)
139 LSL (tmp)
140 LSL (tmp)
141 LSL (tmp)
142 MOV (t, i1)
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143 SWAP (t)
144 ANDI (t, 0xf)
145 LSR (t)
94c4920f 146 OR (t, tmp)
1b023e92 147 #undef tmp
23872091 148 EOR (t, n)
965274e2 149 RCALL g();
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150 LSR (t)
151 LSR (t)
152 ANDI (t, 3)
f28def6a 153 AND (t, s)
46a8d83c 154 ADD (acc, t)
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155
156 //voice 3:
500692e4
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157 MOV (Ml, i2)
158 SWAP (Ml)
159 ANDI (Ml, 0xf0)
160 LSL (Ml)
8ee3310e 161 #define tmp _
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162 MOV (tmp, i1)
163 LSR (tmp)
164 LSR (tmp)
165 LSR (tmp)
166 OR (Ml, tmp)
167 #undef tmp
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168 MOV (Mh, i3)
169 SWAP (Mh)
170 ANDI (Mh, 0xf0)
171 LSL (Mh)
172 #define tmp _
173 MOV (tmp, i2)
174 LSR (tmp)
175 LSR (tmp)
176 LSR (tmp)
177 OR (Mh, tmp)
178 #undef tmp
dbf91c38 179 RCALL mod3();
18570947 180 ADD (t, n)
965274e2 181 RCALL g();
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182 LSR (t)
183 LSR (t)
184 ANDI (t, 3)
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185 MOV (x, s)
186 INC (x)
37bf20ea 187 #define tmp _
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188 MOV (tmp, x)
189 LSR (tmp)
190 LSR (tmp)
191 ADD (tmp, x)
192 ROR (tmp)
193 LSR (tmp)
194 ADD (tmp, x)
195 ROR (tmp)
196 LSR (tmp)
197 ADD (tmp, x)
198 ROR (tmp)
199 LSR (tmp)
51f43293 200 AND (t, tmp)
f28def6a 201 #undef tmp
46a8d83c 202 ADD (acc, t)
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TG
203
204 //voice 4:
649bb224
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205 MOV (Ml, i2)
206 SWAP (Ml)
207 ANDI (Ml, 0xf0)
208 LSL (Ml)
209 LSL (Ml)
8ee3310e 210 #define tmp _
649bb224
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211 MOV (tmp, i1)
212 LSR (tmp)
213 LSR (tmp)
214 OR (Ml, tmp)
215 #undef tmp
18426c43
TG
216 MOV (Mh, i3)
217 SWAP (Mh)
218 ANDI (Mh, 0xf0)
219 LSL (Mh)
220 LSL (Mh)
221 #define tmp _
222 MOV (tmp, i2)
223 LSR (tmp)
224 LSR (tmp)
225 OR (Mh, tmp)
226 #undef tmp
dbf91c38 227 RCALL mod3();
e4f7baf0
TG
228 SUB (t, n)
229 NEG (t)
902cfdea 230 SUBI (t, -8)
965274e2 231 RCALL g();
c6c6cbe5
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232 LSR (t)
233 ANDI (t, 3)
9548359d 234 INC (s)
37bf20ea 235 #define tmp _
9548359d 236 MOV (tmp, s)
d8af0686 237 LSR (tmp)
9548359d 238 ADD (tmp, s)
d8af0686
TG
239 ROR (tmp)
240 LSR (tmp)
241 LSR (tmp)
9548359d 242 ADD (tmp, s)
d8af0686 243 ROR (tmp)
9548359d 244 ADD (tmp, s)
d8af0686
TG
245 ROR (tmp)
246 LSR (tmp)
247 LSR (tmp)
51f43293 248 AND (t, tmp)
d8af0686 249 #undef tmp
46a8d83c 250 ADD (acc, t)
bfce2f8c 251
95fa231f 252 putchar(acc<<4); //TODO
89f35588 253 SUBI (i0, -1)
95fa231f
TG
254 ADC (i1, zero, !i0)
255 ADC (i2, zero, !i0&&!i1)
256 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 257 }
61fab018 258}
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