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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
61592bdd
TG
9u8 zero; //r16
10u8 acc; //r17
11u8 i0; //r18
12u8 i1; //r19
13u8 i2; //r20
14u8 i3; //r21
15u8 n; //r22
16u8 s; //r23
17u8 _; //r24
18 //r25
19u8 t;/*==Ml*/ //r26 (Xlo)
20u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23/*fakestack_l*/ //r30 (Zlo)
24/*fakestack_h*/ //r31 (Zhi)
37bf20ea 25#define Mh x //mod3 vars
dbf91c38 26#define Ml t // -"-
e98ab46f 27//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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28void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
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31 ADD (Ml, Mh)
32 CLR (Mh)
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33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
0e3d0279 39 ANDI (Ml, 0x0f)
2a69999d 40 ADD (Ml, tmp)
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41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
6c72d3c1 44 ANDI (Ml, 0x03)
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45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
c3639d5b
TG
51 CPI (Ml, 3)
52 BRPL (skip)
197a5418 53 SUBI (Ml, 3)
c3639d5b 54 skip:;
4283632d 55 RET
8d8c00e4 56 #undef tmp
e98ab46f 57}
965274e2 58void g(void) {
362b33c9 59 // g(i, t) -> t
eafeaf93 60 // tempvars: `x` and `_`
49137fbf 61 #define tmp _
0f219114 62 ANDI (t, 0x07)
32632e61 63 MOV (tmp, i2)
63363195 64 ANDI (tmp, 3)
09cf3949 65 TST (tmp)
49137fbf 66 #undef tmp
09cf3949
TG
67 BREQ (skip)
68 SUBI (t, -8)
69 skip:
c616f0c2 70 t = data[t];
8ee3310e 71 /*MOV X_hi==x, data_hi
49137fbf
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72 MOV X_lo==t, data_lo
73 ADD X_lo, t
49137fbf
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74 ADC X_hi, zero
75 LD t, X */
5700437a
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76 #define a1 x
77 #define a2 _
d397f897 78 #define a0 t
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79 CLR (a2)
80 CLR (a1)
d397f897 81 for (u8 loop = 0; loop < 8; loop++) { //Note: t&2 always zero
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82 SBRS (t, 0)
83 goto skip2;
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84 ADD (a1, i0)
85 ADC (a2, i1, carry)
7b96a97d 86 skip2:
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87 LSR (a2)
88 ROR (a1)
89 ROR (t)
d397f897 90 }
27ca59e7 91 MOV (t, a1) //can't return x or _ as a1, both needed later besides t
5700437a 92 #undef a0
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93 #undef a1
94 #undef a2
d397f897 95
d5b74a12 96 RET //TODO: replace CALL/RET with IJMP?
61fab018
TG
97};
98
99int main(void) {
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100 CLR (zero)
101 CLR (i0)
102 CLR (i1)
103 CLR (i2)
104 CLR (i3)
5dd8b8ff 105 for (;;) {
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106 MOV (n, i2)
107 LSL (n)
108 LSL (n)
8ee3310e 109 #define tmp _
bc7680e3 110 MOV (tmp, i1)
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111 SWAP (tmp)
112 ANDI (tmp, 0x0f)
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113 LSR (tmp)
114 LSR (tmp)
128ff01a 115 OR (n, tmp)
bc7680e3 116 #undef tmp
df192822 117 MOV (s, i3)
2bbe001f 118 LSR (s)
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119 ROR (s)
120 ANDI (s, 0x80)
8ee3310e 121 #define tmp _
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122 MOV (tmp, i2)
123 LSR (tmp)
e389879f 124 OR (s, tmp)
df192822 125 #undef tmp
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126
127 //voice 1:
3b86ca43 128 MOV (t, n)
965274e2 129 RCALL g();
c09a6ed8 130 SWAP (t)
9e62fea4 131 ANDI (t, 1)
46a8d83c 132 MOV (acc, t)
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133
134 //voice 2:
37bf20ea 135 #define tmp _
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136 MOV (tmp, i2)
137 LSL (tmp)
138 LSL (tmp)
139 LSL (tmp)
140 MOV (t, i1)
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141 SWAP (t)
142 ANDI (t, 0xf)
143 LSR (t)
94c4920f 144 OR (t, tmp)
1b023e92 145 #undef tmp
23872091 146 EOR (t, n)
965274e2 147 RCALL g();
7716b427
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148 LSR (t)
149 LSR (t)
150 ANDI (t, 3)
f28def6a 151 AND (t, s)
46a8d83c 152 ADD (acc, t)
3b86ca43
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153
154 //voice 3:
500692e4
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155 MOV (Ml, i2)
156 SWAP (Ml)
157 ANDI (Ml, 0xf0)
158 LSL (Ml)
8ee3310e 159 #define tmp _
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160 MOV (tmp, i1)
161 LSR (tmp)
162 LSR (tmp)
163 LSR (tmp)
164 OR (Ml, tmp)
165 #undef tmp
d39a46f5
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166 MOV (Mh, i3)
167 SWAP (Mh)
168 ANDI (Mh, 0xf0)
169 LSL (Mh)
170 #define tmp _
171 MOV (tmp, i2)
172 LSR (tmp)
173 LSR (tmp)
174 LSR (tmp)
175 OR (Mh, tmp)
176 #undef tmp
dbf91c38 177 RCALL mod3();
18570947 178 ADD (t, n)
965274e2 179 RCALL g();
c6c6cbe5
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180 LSR (t)
181 LSR (t)
182 ANDI (t, 3)
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183 MOV (x, s)
184 INC (x)
37bf20ea 185 #define tmp _
f28def6a
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186 MOV (tmp, x)
187 LSR (tmp)
188 LSR (tmp)
189 ADD (tmp, x)
190 ROR (tmp)
191 LSR (tmp)
192 ADD (tmp, x)
193 ROR (tmp)
194 LSR (tmp)
195 ADD (tmp, x)
196 ROR (tmp)
197 LSR (tmp)
51f43293 198 AND (t, tmp)
f28def6a 199 #undef tmp
46a8d83c 200 ADD (acc, t)
3b86ca43
TG
201
202 //voice 4:
649bb224
TG
203 MOV (Ml, i2)
204 SWAP (Ml)
205 ANDI (Ml, 0xf0)
206 LSL (Ml)
207 LSL (Ml)
8ee3310e 208 #define tmp _
649bb224
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209 MOV (tmp, i1)
210 LSR (tmp)
211 LSR (tmp)
212 OR (Ml, tmp)
213 #undef tmp
18426c43
TG
214 MOV (Mh, i3)
215 SWAP (Mh)
216 ANDI (Mh, 0xf0)
217 LSL (Mh)
218 LSL (Mh)
219 #define tmp _
220 MOV (tmp, i2)
221 LSR (tmp)
222 LSR (tmp)
223 OR (Mh, tmp)
224 #undef tmp
dbf91c38 225 RCALL mod3();
e4f7baf0
TG
226 SUB (t, n)
227 NEG (t)
902cfdea 228 SUBI (t, -8)
965274e2 229 RCALL g();
c6c6cbe5
TG
230 LSR (t)
231 ANDI (t, 3)
9548359d 232 INC (s)
37bf20ea 233 #define tmp _
9548359d 234 MOV (tmp, s)
d8af0686 235 LSR (tmp)
9548359d 236 ADD (tmp, s)
d8af0686
TG
237 ROR (tmp)
238 LSR (tmp)
239 LSR (tmp)
9548359d 240 ADD (tmp, s)
d8af0686 241 ROR (tmp)
9548359d 242 ADD (tmp, s)
d8af0686
TG
243 ROR (tmp)
244 LSR (tmp)
245 LSR (tmp)
51f43293 246 AND (t, tmp)
d8af0686 247 #undef tmp
46a8d83c 248 ADD (acc, t)
bfce2f8c 249
95fa231f 250 putchar(acc<<4); //TODO
89f35588 251 SUBI (i0, -1)
95fa231f
TG
252 ADC (i1, zero, !i0)
253 ADC (i2, zero, !i0&&!i1)
254 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 255 }
61fab018 256}
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