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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
61592bdd
TG
9u8 zero; //r16
10u8 acc; //r17
11u8 i0; //r18
12u8 i1; //r19
13u8 i2; //r20
14u8 i3; //r21
15u8 n; //r22
16u8 s; //r23
17u8 _; //r24
181efc5e 18u8 loop; //r25
61592bdd
TG
19u8 t;/*==Ml*/ //r26 (Xlo)
20u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23/*fakestack_l*/ //r30 (Zlo)
24/*fakestack_h*/ //r31 (Zhi)
37bf20ea 25#define Mh x //mod3 vars
dbf91c38 26#define Ml t // -"-
e98ab46f 27//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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28void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
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31 ADD (Ml, Mh)
32 CLR (Mh)
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33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
0e3d0279 39 ANDI (Ml, 0x0f)
2a69999d 40 ADD (Ml, tmp)
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41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
6c72d3c1 44 ANDI (Ml, 0x03)
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45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
c3639d5b
TG
51 CPI (Ml, 3)
52 BRPL (skip)
197a5418 53 SUBI (Ml, 3)
c3639d5b 54 skip:;
4283632d 55 RET
8d8c00e4 56 #undef tmp
e98ab46f 57}
d0324785
TG
58void mul(void) { //don't need overhead of function (inline it)
59 // i1.i0 * t -> _.x.t
60 #define a1 x
61 #define a2 _
62 #define a0 t
63 // start MUL -- 92 cycles :( (unrolled and skipping second bit: 76)
64 CLR (a2)
65 CLR (a1)
66
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67 switch(t) {
68 case 0x58: // 0101 1000
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69 LSR (a2)
70 ROR (a1)
71 LSR (a2)
72 ROR (a1)
73 LSR (a2)
74 ROR (a1)
75 ADD (a1, i0)
76 ADC (a2, i1, carry)
77 LSR (a2)
78 ROR (a1)
d0324785 79
30966f17
TG
80 ADD (a1, i0)
81 ADC (a2, i1, carry)
82 LSR (a2)
83 ROR (a1)
84 LSR (a2)
85 ROR (a1)
86 ADD (a1, i0)
87 ADC (a2, i1, carry)
88 LSR (a2)
89 ROR (a1)
90 LSR (a2)
91 ROR (a1)
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92 break;
93 case 0x69: // 0110 1001
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94 ADD (a1, i0)
95 ADC (a2, i1, carry)
96 LSR (a2)
97 ROR (a1)
98 LSR (a2)
99 ROR (a1)
100 LSR (a2)
101 ROR (a1)
102 ADD (a1, i0)
103 ADC (a2, i1, carry)
104 LSR (a2)
105 ROR (a1)
d0324785 106
30966f17
TG
107 LSR (a2)
108 ROR (a1)
109 ADD (a1, i0)
110 ADC (a2, i1, carry)
111 LSR (a2)
112 ROR (a1)
113 ADD (a1, i0)
114 ADC (a2, i1, carry)
115 LSR (a2)
116 ROR (a1)
117 LSR (a2)
118 ROR (a1)
d0324785
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119 break;
120 case 0x75: // 0111 0101
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121 ADD (a1, i0)
122 ADC (a2, i1, carry)
123 LSR (a2)
124 ROR (a1)
125 LSR (a2)
126 ROR (a1)
127 ADD (a1, i0)
128 ADC (a2, i1, carry)
129 LSR (a2)
130 ROR (a1)
131 LSR (a2)
132 ROR (a1)
d0324785 133
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TG
134 ADD (a1, i0)
135 ADC (a2, i1, carry)
136 LSR (a2)
137 ROR (a1)
138 ADD (a1, i0)
139 ADC (a2, i1, carry)
140 LSR (a2)
141 ROR (a1)
142 ADD (a1, i0)
143 ADC (a2, i1, carry)
144 LSR (a2)
145 ROR (a1)
146 LSR (a2)
147 ROR (a1)
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148 break;
149 case 0x84: // 1000 0100
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150 LSR (a2)
151 ROR (a1)
152 LSR (a2)
153 ROR (a1)
154 ADD (a1, i0)
155 ADC (a2, i1, carry)
156 LSR (a2)
157 ROR (a1)
158 LSR (a2)
159 ROR (a1)
d0324785 160
30966f17
TG
161 LSR (a2)
162 ROR (a1)
163 LSR (a2)
164 ROR (a1)
165 LSR (a2)
166 ROR (a1)
167 ADD (a1, i0)
168 ADC (a2, i1, carry)
169 LSR (a2)
170 ROR (a1)
d0324785
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171 break;
172 case 0x8c: // 1000 1100
30966f17
TG
173 LSR (a2)
174 ROR (a1)
175 LSR (a2)
176 ROR (a1)
177 ADD (a1, i0)
178 ADC (a2, i1, carry)
179 LSR (a2)
180 ROR (a1)
181 ADD (a1, i0)
182 ADC (a2, i1, carry)
183 LSR (a2)
184 ROR (a1)
d0324785 185
30966f17
TG
186 LSR (a2)
187 ROR (a1)
188 LSR (a2)
189 ROR (a1)
190 LSR (a2)
191 ROR (a1)
192 ADD (a1, i0)
193 ADC (a2, i1, carry)
194 LSR (a2)
195 ROR (a1)
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196 break;
197 case 0x9d: // 1001 1101
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198 ADD (a1, i0)
199 ADC (a2, i1, carry)
200 LSR (a2)
201 ROR (a1)
202 LSR (a2)
203 ROR (a1)
204 ADD (a1, i0)
205 ADC (a2, i1, carry)
206 LSR (a2)
207 ROR (a1)
208 ADD (a1, i0)
209 ADC (a2, i1, carry)
210 LSR (a2)
211 ROR (a1)
d0324785 212
30966f17
TG
213 ADD (a1, i0)
214 ADC (a2, i1, carry)
215 LSR (a2)
216 ROR (a1)
217 LSR (a2)
218 ROR (a1)
219 LSR (a2)
220 ROR (a1)
221 ADD (a1, i0)
222 ADC (a2, i1, carry)
223 LSR (a2)
224 ROR (a1)
d0324785
TG
225 break;
226 case 0xb0: // 1011 0000
30966f17
TG
227 LSR (a2)
228 ROR (a1)
229 LSR (a2)
230 ROR (a1)
231 LSR (a2)
232 ROR (a1)
233 LSR (a2)
234 ROR (a1)
d0324785 235
30966f17
TG
236 ADD (a1, i0)
237 ADC (a2, i1, carry)
238 LSR (a2)
239 ROR (a1)
240 ADD (a1, i0)
241 ADC (a2, i1, carry)
242 LSR (a2)
243 ROR (a1)
244 LSR (a2)
245 ROR (a1)
246 ADD (a1, i0)
247 ADC (a2, i1, carry)
248 LSR (a2)
249 ROR (a1)
d0324785
TG
250 }
251
252 // end MUL
253 #undef a0
254 #undef a1
255 #undef a2
256 RET
257}
965274e2 258void g(void) {
362b33c9 259 // g(i, t) -> t
eafeaf93 260 // tempvars: `x` and `_`
49137fbf 261 #define tmp _
0f219114 262 ANDI (t, 0x07)
32632e61 263 MOV (tmp, i2)
63363195 264 ANDI (tmp, 3)
09cf3949 265 TST (tmp)
49137fbf 266 #undef tmp
09cf3949
TG
267 BREQ (skip)
268 SUBI (t, -8)
269 skip:
c616f0c2 270 t = data[t];
8ee3310e 271 /*MOV X_hi==x, data_hi
49137fbf
TG
272 MOV X_lo==t, data_lo
273 ADD X_lo, t
49137fbf
TG
274 ADC X_hi, zero
275 LD t, X */
d0324785
TG
276 RCALL mul(); //stores used value in in x
277 MOV (t, x)
d5b74a12 278 RET //TODO: replace CALL/RET with IJMP?
61fab018
TG
279};
280
281int main(void) {
23e66ca4
TG
282 CLR (zero)
283 CLR (i0)
284 CLR (i1)
285 CLR (i2)
286 CLR (i3)
5dd8b8ff 287 for (;;) {
7874ed03
TG
288 MOV (n, i2)
289 LSL (n)
290 LSL (n)
8ee3310e 291 #define tmp _
bc7680e3 292 MOV (tmp, i1)
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TG
293 SWAP (tmp)
294 ANDI (tmp, 0x0f)
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TG
295 LSR (tmp)
296 LSR (tmp)
128ff01a 297 OR (n, tmp)
bc7680e3 298 #undef tmp
df192822 299 MOV (s, i3)
2bbe001f 300 LSR (s)
27b03017
TG
301 ROR (s)
302 ANDI (s, 0x80)
8ee3310e 303 #define tmp _
a582bbc3
TG
304 MOV (tmp, i2)
305 LSR (tmp)
e389879f 306 OR (s, tmp)
df192822 307 #undef tmp
3b86ca43
TG
308
309 //voice 1:
3b86ca43 310 MOV (t, n)
965274e2 311 RCALL g();
c09a6ed8 312 SWAP (t)
9e62fea4 313 ANDI (t, 1)
46a8d83c 314 MOV (acc, t)
3b86ca43
TG
315
316 //voice 2:
37bf20ea 317 #define tmp _
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TG
318 MOV (tmp, i2)
319 LSL (tmp)
320 LSL (tmp)
321 LSL (tmp)
322 MOV (t, i1)
4b0b7dc5
TG
323 SWAP (t)
324 ANDI (t, 0xf)
325 LSR (t)
94c4920f 326 OR (t, tmp)
1b023e92 327 #undef tmp
23872091 328 EOR (t, n)
965274e2 329 RCALL g();
7716b427
TG
330 LSR (t)
331 LSR (t)
332 ANDI (t, 3)
f28def6a 333 AND (t, s)
46a8d83c 334 ADD (acc, t)
3b86ca43
TG
335
336 //voice 3:
500692e4
TG
337 MOV (Ml, i2)
338 SWAP (Ml)
339 ANDI (Ml, 0xf0)
340 LSL (Ml)
8ee3310e 341 #define tmp _
500692e4
TG
342 MOV (tmp, i1)
343 LSR (tmp)
344 LSR (tmp)
345 LSR (tmp)
346 OR (Ml, tmp)
347 #undef tmp
d39a46f5
TG
348 MOV (Mh, i3)
349 SWAP (Mh)
350 ANDI (Mh, 0xf0)
351 LSL (Mh)
352 #define tmp _
353 MOV (tmp, i2)
354 LSR (tmp)
355 LSR (tmp)
356 LSR (tmp)
357 OR (Mh, tmp)
358 #undef tmp
dbf91c38 359 RCALL mod3();
18570947 360 ADD (t, n)
965274e2 361 RCALL g();
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362 LSR (t)
363 LSR (t)
364 ANDI (t, 3)
f28def6a
TG
365 MOV (x, s)
366 INC (x)
37bf20ea 367 #define tmp _
f28def6a
TG
368 MOV (tmp, x)
369 LSR (tmp)
370 LSR (tmp)
371 ADD (tmp, x)
372 ROR (tmp)
373 LSR (tmp)
374 ADD (tmp, x)
375 ROR (tmp)
376 LSR (tmp)
377 ADD (tmp, x)
378 ROR (tmp)
379 LSR (tmp)
51f43293 380 AND (t, tmp)
f28def6a 381 #undef tmp
46a8d83c 382 ADD (acc, t)
3b86ca43
TG
383
384 //voice 4:
649bb224
TG
385 MOV (Ml, i2)
386 SWAP (Ml)
387 ANDI (Ml, 0xf0)
388 LSL (Ml)
389 LSL (Ml)
8ee3310e 390 #define tmp _
649bb224
TG
391 MOV (tmp, i1)
392 LSR (tmp)
393 LSR (tmp)
394 OR (Ml, tmp)
395 #undef tmp
18426c43
TG
396 MOV (Mh, i3)
397 SWAP (Mh)
398 ANDI (Mh, 0xf0)
399 LSL (Mh)
400 LSL (Mh)
401 #define tmp _
402 MOV (tmp, i2)
403 LSR (tmp)
404 LSR (tmp)
405 OR (Mh, tmp)
406 #undef tmp
dbf91c38 407 RCALL mod3();
e4f7baf0
TG
408 SUB (t, n)
409 NEG (t)
902cfdea 410 SUBI (t, -8)
965274e2 411 RCALL g();
c6c6cbe5
TG
412 LSR (t)
413 ANDI (t, 3)
9548359d 414 INC (s)
37bf20ea 415 #define tmp _
9548359d 416 MOV (tmp, s)
d8af0686 417 LSR (tmp)
9548359d 418 ADD (tmp, s)
d8af0686
TG
419 ROR (tmp)
420 LSR (tmp)
421 LSR (tmp)
9548359d 422 ADD (tmp, s)
d8af0686 423 ROR (tmp)
9548359d 424 ADD (tmp, s)
d8af0686
TG
425 ROR (tmp)
426 LSR (tmp)
427 LSR (tmp)
51f43293 428 AND (t, tmp)
d8af0686 429 #undef tmp
46a8d83c 430 ADD (acc, t)
bfce2f8c 431
95fa231f 432 putchar(acc<<4); //TODO
89f35588 433 SUBI (i0, -1)
95fa231f
TG
434 ADC (i1, zero, !i0)
435 ADC (i2, zero, !i0&&!i1)
436 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 437 }
61fab018 438}
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