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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
61592bdd
TG
9u8 zero; //r16
10u8 acc; //r17
11u8 i0; //r18
12u8 i1; //r19
13u8 i2; //r20
14u8 i3; //r21
15u8 n; //r22
16u8 s; //r23
17u8 _; //r24
181efc5e 18u8 loop; //r25
61592bdd
TG
19u8 t;/*==Ml*/ //r26 (Xlo)
20u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23/*fakestack_l*/ //r30 (Zlo)
24/*fakestack_h*/ //r31 (Zhi)
37bf20ea 25#define Mh x //mod3 vars
dbf91c38 26#define Ml t // -"-
e98ab46f 27//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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TG
28void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
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31 ADD (Ml, Mh)
32 CLR (Mh)
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33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
0e3d0279 39 ANDI (Ml, 0x0f)
2a69999d 40 ADD (Ml, tmp)
0fc1d6d3
TG
41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
6c72d3c1 44 ANDI (Ml, 0x03)
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TG
45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
c3639d5b
TG
51 CPI (Ml, 3)
52 BRPL (skip)
197a5418 53 SUBI (Ml, 3)
c3639d5b 54 skip:;
4283632d 55 RET
8d8c00e4 56 #undef tmp
e98ab46f 57}
d0324785
TG
58void mul(void) { //don't need overhead of function (inline it)
59 // i1.i0 * t -> _.x.t
60 #define a1 x
61 #define a2 _
62 #define a0 t
63 // start MUL -- 92 cycles :( (unrolled and skipping second bit: 76)
64 CLR (a2)
65 CLR (a1)
66
67 #define MUL_ADD_ROR \
68 ADD (a1, i0) \
69 ADC (a2, i1, carry) \
70 MUL_ROR
71
72 #define MUL_ROR \
73 LSR (a2) \
317ff90d 74 ROR (a1)
d0324785
TG
75
76 switch(t) {
77 case 0x58: // 0101 1000
78 MUL_ROR
79 MUL_ROR
80 MUL_ROR
81 MUL_ADD_ROR
82
83 MUL_ADD_ROR
84 MUL_ROR
85 MUL_ADD_ROR
86 MUL_ROR
87 break;
88 case 0x69: // 0110 1001
89 MUL_ADD_ROR
90 MUL_ROR
91 MUL_ROR
92 MUL_ADD_ROR
93
94 MUL_ROR
95 MUL_ADD_ROR
96 MUL_ADD_ROR
97 MUL_ROR
98 break;
99 case 0x75: // 0111 0101
100 MUL_ADD_ROR
101 MUL_ROR
102 MUL_ADD_ROR
103 MUL_ROR
104
105 MUL_ADD_ROR
106 MUL_ADD_ROR
107 MUL_ADD_ROR
108 MUL_ROR
109 break;
110 case 0x84: // 1000 0100
111 MUL_ROR
112 MUL_ROR
113 MUL_ADD_ROR
114 MUL_ROR
115
116 MUL_ROR
117 MUL_ROR
118 MUL_ROR
119 MUL_ADD_ROR
120 break;
121 case 0x8c: // 1000 1100
122 MUL_ROR
123 MUL_ROR
124 MUL_ADD_ROR
125 MUL_ADD_ROR
126
127 MUL_ROR
128 MUL_ROR
129 MUL_ROR
130 MUL_ADD_ROR
131 break;
132 case 0x9d: // 1001 1101
133 MUL_ADD_ROR
134 MUL_ROR
135 MUL_ADD_ROR
136 MUL_ADD_ROR
137
138 MUL_ADD_ROR
139 MUL_ROR
140 MUL_ROR
141 MUL_ADD_ROR
142 break;
143 case 0xb0: // 1011 0000
144 MUL_ROR
145 MUL_ROR
146 MUL_ROR
147 MUL_ROR
148
149 MUL_ADD_ROR
150 MUL_ADD_ROR
151 MUL_ROR
152 MUL_ADD_ROR
153 }
154
155 // end MUL
156 #undef a0
157 #undef a1
158 #undef a2
159 RET
160}
965274e2 161void g(void) {
362b33c9 162 // g(i, t) -> t
eafeaf93 163 // tempvars: `x` and `_`
49137fbf 164 #define tmp _
0f219114 165 ANDI (t, 0x07)
32632e61 166 MOV (tmp, i2)
63363195 167 ANDI (tmp, 3)
09cf3949 168 TST (tmp)
49137fbf 169 #undef tmp
09cf3949
TG
170 BREQ (skip)
171 SUBI (t, -8)
172 skip:
c616f0c2 173 t = data[t];
8ee3310e 174 /*MOV X_hi==x, data_hi
49137fbf
TG
175 MOV X_lo==t, data_lo
176 ADD X_lo, t
49137fbf
TG
177 ADC X_hi, zero
178 LD t, X */
d0324785
TG
179 RCALL mul(); //stores used value in in x
180 MOV (t, x)
d5b74a12 181 RET //TODO: replace CALL/RET with IJMP?
61fab018
TG
182};
183
184int main(void) {
23e66ca4
TG
185 CLR (zero)
186 CLR (i0)
187 CLR (i1)
188 CLR (i2)
189 CLR (i3)
5dd8b8ff 190 for (;;) {
7874ed03
TG
191 MOV (n, i2)
192 LSL (n)
193 LSL (n)
8ee3310e 194 #define tmp _
bc7680e3 195 MOV (tmp, i1)
5d4207f9
TG
196 SWAP (tmp)
197 ANDI (tmp, 0x0f)
3eef1ade
TG
198 LSR (tmp)
199 LSR (tmp)
128ff01a 200 OR (n, tmp)
bc7680e3 201 #undef tmp
df192822 202 MOV (s, i3)
2bbe001f 203 LSR (s)
27b03017
TG
204 ROR (s)
205 ANDI (s, 0x80)
8ee3310e 206 #define tmp _
a582bbc3
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207 MOV (tmp, i2)
208 LSR (tmp)
e389879f 209 OR (s, tmp)
df192822 210 #undef tmp
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211
212 //voice 1:
3b86ca43 213 MOV (t, n)
965274e2 214 RCALL g();
c09a6ed8 215 SWAP (t)
9e62fea4 216 ANDI (t, 1)
46a8d83c 217 MOV (acc, t)
3b86ca43
TG
218
219 //voice 2:
37bf20ea 220 #define tmp _
94c4920f
TG
221 MOV (tmp, i2)
222 LSL (tmp)
223 LSL (tmp)
224 LSL (tmp)
225 MOV (t, i1)
4b0b7dc5
TG
226 SWAP (t)
227 ANDI (t, 0xf)
228 LSR (t)
94c4920f 229 OR (t, tmp)
1b023e92 230 #undef tmp
23872091 231 EOR (t, n)
965274e2 232 RCALL g();
7716b427
TG
233 LSR (t)
234 LSR (t)
235 ANDI (t, 3)
f28def6a 236 AND (t, s)
46a8d83c 237 ADD (acc, t)
3b86ca43
TG
238
239 //voice 3:
500692e4
TG
240 MOV (Ml, i2)
241 SWAP (Ml)
242 ANDI (Ml, 0xf0)
243 LSL (Ml)
8ee3310e 244 #define tmp _
500692e4
TG
245 MOV (tmp, i1)
246 LSR (tmp)
247 LSR (tmp)
248 LSR (tmp)
249 OR (Ml, tmp)
250 #undef tmp
d39a46f5
TG
251 MOV (Mh, i3)
252 SWAP (Mh)
253 ANDI (Mh, 0xf0)
254 LSL (Mh)
255 #define tmp _
256 MOV (tmp, i2)
257 LSR (tmp)
258 LSR (tmp)
259 LSR (tmp)
260 OR (Mh, tmp)
261 #undef tmp
dbf91c38 262 RCALL mod3();
18570947 263 ADD (t, n)
965274e2 264 RCALL g();
c6c6cbe5
TG
265 LSR (t)
266 LSR (t)
267 ANDI (t, 3)
f28def6a
TG
268 MOV (x, s)
269 INC (x)
37bf20ea 270 #define tmp _
f28def6a
TG
271 MOV (tmp, x)
272 LSR (tmp)
273 LSR (tmp)
274 ADD (tmp, x)
275 ROR (tmp)
276 LSR (tmp)
277 ADD (tmp, x)
278 ROR (tmp)
279 LSR (tmp)
280 ADD (tmp, x)
281 ROR (tmp)
282 LSR (tmp)
51f43293 283 AND (t, tmp)
f28def6a 284 #undef tmp
46a8d83c 285 ADD (acc, t)
3b86ca43
TG
286
287 //voice 4:
649bb224
TG
288 MOV (Ml, i2)
289 SWAP (Ml)
290 ANDI (Ml, 0xf0)
291 LSL (Ml)
292 LSL (Ml)
8ee3310e 293 #define tmp _
649bb224
TG
294 MOV (tmp, i1)
295 LSR (tmp)
296 LSR (tmp)
297 OR (Ml, tmp)
298 #undef tmp
18426c43
TG
299 MOV (Mh, i3)
300 SWAP (Mh)
301 ANDI (Mh, 0xf0)
302 LSL (Mh)
303 LSL (Mh)
304 #define tmp _
305 MOV (tmp, i2)
306 LSR (tmp)
307 LSR (tmp)
308 OR (Mh, tmp)
309 #undef tmp
dbf91c38 310 RCALL mod3();
e4f7baf0
TG
311 SUB (t, n)
312 NEG (t)
902cfdea 313 SUBI (t, -8)
965274e2 314 RCALL g();
c6c6cbe5
TG
315 LSR (t)
316 ANDI (t, 3)
9548359d 317 INC (s)
37bf20ea 318 #define tmp _
9548359d 319 MOV (tmp, s)
d8af0686 320 LSR (tmp)
9548359d 321 ADD (tmp, s)
d8af0686
TG
322 ROR (tmp)
323 LSR (tmp)
324 LSR (tmp)
9548359d 325 ADD (tmp, s)
d8af0686 326 ROR (tmp)
9548359d 327 ADD (tmp, s)
d8af0686
TG
328 ROR (tmp)
329 LSR (tmp)
330 LSR (tmp)
51f43293 331 AND (t, tmp)
d8af0686 332 #undef tmp
46a8d83c 333 ADD (acc, t)
bfce2f8c 334
95fa231f 335 putchar(acc<<4); //TODO
89f35588 336 SUBI (i0, -1)
95fa231f
TG
337 ADC (i1, zero, !i0)
338 ADC (i2, zero, !i0&&!i1)
339 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 340 }
61fab018 341}
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