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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
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5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
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10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
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14u8 x;
15u8 t;
16u8 o;
49137fbf 17u8 _;
e98ab46f 18#define Mh o //mod3 vars
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19#define Ml t // -"-
20void mod3(void) { //avail: t, o _
e98ab46f 21//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
5b1c6cc5 22 #define tmp _
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23 ADD (Ml, Mh)
24 CLR (Mh)
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25 ADC (Mh, zero, carry) //Mh only holds the carry bit
26 MOV (tmp, Ml)
27 SWAP (tmp)
28 ANDI (tmp, 0x0f)
29 SWAP (Mh)
30 OR (tmp, Mh)
31 Ml = (tmp) + (Ml & 0xF);
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32 Ml = (Ml >> 2) + (Ml & 0x3);
33 Ml = (Ml >> 2) + (Ml & 0x3);
34 if (Ml > 2) Ml = Ml - 3;
5b1c6cc5 35 #undef tmp
e98ab46f 36}
965274e2 37void g(void) {
46a8d83c 38 // g(i, x, t, o) -> t
49137fbf 39 #define tmp _
0f219114 40 ANDI (t, 0x07)
32632e61 41 MOV (tmp, i2)
63363195 42 ANDI (tmp, 3)
09cf3949 43 TST (tmp)
49137fbf 44 #undef tmp
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45 BREQ (skip)
46 SUBI (t, -8)
47 skip:
c616f0c2 48 t = data[t];
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49 /*MOV X_hi==_, data_hi
50 MOV X_lo==t, data_lo
51 ADD X_lo, t
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52 ADC X_hi, zero
53 LD t, X */
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54 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
55 t >>= o; //NOTE: o == {1, 2, 4}
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56 AND (t, x)
57 ANDI (t, 3)
46a8d83c 58 RET
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59};
60
61int main(void) {
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62 u8 n;
63 u8 s;
ab6fe4c2 64 u8 acc;
89f35588 65 //TODO: clear all vars/registers
5dd8b8ff 66 for (;;) {
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67 MOV (n, i2)
68 LSL (n)
69 LSL (n)
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70 #define tmp acc
71 MOV (tmp, i1)
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72 SWAP (tmp)
73 ANDI (tmp, 0x0f)
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74 LSR (tmp)
75 LSR (tmp)
128ff01a 76 OR (n, tmp)
bc7680e3 77 #undef tmp
df192822 78 MOV (s, i3)
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79 ROR (s)
80 ROR (s)
81 ANDI (s, 0x80)
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82 #define tmp acc
83 MOV (tmp, i2)
84 LSR (tmp)
e389879f 85 OR (s, tmp)
df192822 86 #undef tmp
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87
88 //voice 1:
89 LDI (x, 1)
90 MOV (t, n)
9401049b 91 LDI (o, 4)
965274e2 92 RCALL g();
46a8d83c 93 MOV (acc, t)
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94
95 //voice 2:
96 MOV (x, s)
1b023e92 97 #define tmp o
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98 MOV (tmp, i2)
99 LSL (tmp)
100 LSL (tmp)
101 LSL (tmp)
102 MOV (t, i1)
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103 SWAP (t)
104 ANDI (t, 0xf)
105 LSR (t)
94c4920f 106 OR (t, tmp)
1b023e92 107 #undef tmp
23872091 108 EOR (t, n)
9401049b 109 LDI (o, 2)
965274e2 110 RCALL g();
46a8d83c 111 ADD (acc, t)
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112
113 //voice 3:
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114 MOV (x, s)
115 INC (x)
17c5b4e9 116 #define tmp o
a7a7abba 117 MOV (tmp, x)
f84bcb7f 118 LSR (tmp)
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119 LSR (tmp)
120 ADD (tmp, x)
121 ROR (tmp)
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122 LSR (tmp)
123 ADD (tmp, x)
124 ROR (tmp)
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125 LSR (tmp)
126 ADD (tmp, x)
127 ROR (tmp)
546b5bab 128 LSR (tmp)
2c94c801 129 MOV (x, tmp)
17c5b4e9 130 #undef tmp
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131 Ml = i2<<5 | i1>>3;
132 Mh = i3<<5 | i2>>3;
dbf91c38 133 RCALL mod3();
18570947 134 ADD (t, n)
9401049b 135 LDI (o, 2)
965274e2 136 RCALL g();
46a8d83c 137 ADD (acc, t)
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138
139 //voice 4:
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140 MOV (x, s)
141 INC (x)
142 #define tmp o
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143 MOV (tmp, x)
144 LSR (tmp)
145 ADD (tmp, x)
146 ROR (tmp)
86f35aa4 147 LSR (tmp)
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148 LSR (tmp)
149 ADD (tmp, x)
150 ROR (tmp)
151 ADD (tmp, x)
152 ROR (tmp)
86f35aa4 153 LSR (tmp)
86f35aa4 154 LSR (tmp)
c2693411 155 MOV (x, tmp)
6bc3ca83 156 #undef tmp
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157 Ml = i2<<6 | i1>>2;
158 Mh = i3<<6 | i2>>2;
dbf91c38 159 RCALL mod3();
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160 SUB (t, n)
161 NEG (t)
902cfdea 162 SUBI (t, -8)
9401049b 163 LDI (o, 1)
965274e2 164 RCALL g();
46a8d83c 165 ADD (acc, t)
bfce2f8c 166
95fa231f 167 putchar(acc<<4); //TODO
89f35588 168 SUBI (i0, -1)
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169 ADC (i1, zero, !i0)
170 ADC (i2, zero, !i0&&!i1)
171 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 172 }
61fab018 173}
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