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[Chiptunes.git] / foo.c
CommitLineData
61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
06aad1ff
TG
9u8 i0;
10u8 i1;
11u8 i2;
12u8 i3;
3b86ca43
TG
13u8 x;
14u8 t;
15u8 o;
965274e2 16void g(void) {
46a8d83c 17 // g(i, x, t, o) -> t
63363195 18 u8 tmp;
0f219114 19 ANDI (t, 0x07)
32632e61 20 MOV (tmp, i2)
63363195 21 ANDI (tmp, 3)
09cf3949
TG
22 TST (tmp)
23 BREQ (skip)
24 SUBI (t, -8)
25 skip:
c616f0c2 26 t = data[t];
965274e2 27 t = ((i3<<24|i2<<16|i1<<8|i0)*t) >> o;
c616f0c2
TG
28 AND (t, x)
29 ANDI (t, 3)
46a8d83c 30 RET
61fab018
TG
31};
32
33int main(void) {
a1631438
TG
34 u8 n;
35 u8 s;
ab6fe4c2 36 u8 acc;
89f35588 37 //TODO: clear all vars/registers
5dd8b8ff 38 for (;;) {
7874ed03
TG
39 MOV (n, i2)
40 LSL (n)
41 LSL (n)
bc7680e3
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42 #define tmp acc
43 MOV (tmp, i1)
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TG
44 SWAP (tmp)
45 ANDI (tmp, 0x0f)
3eef1ade
TG
46 LSR (tmp)
47 LSR (tmp)
128ff01a 48 OR (n, tmp)
bc7680e3 49 #undef tmp
b67a2de3 50 s = (i3<<7 | i2>>1);
3b86ca43
TG
51
52 //voice 1:
53 LDI (x, 1)
54 MOV (t, n)
55 LDI (o, 12)
965274e2 56 RCALL g();
46a8d83c 57 MOV (acc, t)
3b86ca43
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58
59 //voice 2:
60 MOV (x, s)
1b023e92 61 #define tmp o
94c4920f
TG
62 MOV (tmp, i2)
63 LSL (tmp)
64 LSL (tmp)
65 LSL (tmp)
66 MOV (t, i1)
4b0b7dc5
TG
67 SWAP (t)
68 ANDI (t, 0xf)
69 LSR (t)
94c4920f 70 OR (t, tmp)
1b023e92 71 #undef tmp
23872091 72 EOR (t, n)
3b86ca43 73 LDI (o, 10)
965274e2 74 RCALL g();
46a8d83c 75 ADD (acc, t)
3b86ca43
TG
76
77 //voice 3:
78 x = s / 3;
d9218a18 79 t = n + ((i3<<13 | i2<<5 | i1>>3) % 3);
3b86ca43 80 LDI (o, 10)
965274e2 81 RCALL g();
46a8d83c 82 ADD (acc, t)
3b86ca43
TG
83
84 //voice 4:
85 x = s / 5;
704b11ab 86 t = 8 + n - ((i3<<14 | i2<<6 | i1>>2) % 3);
3b86ca43 87 LDI (o, 9)
965274e2 88 RCALL g();
46a8d83c 89 ADD (acc, t)
bfce2f8c 90
ab6fe4c2 91 putchar(acc<<4);
89f35588
TG
92 #define tmp acc
93 LDI (tmp, 0)
94 SUBI (i0, -1)
95 ADC (i1, tmp, !i0)
96 ADC (i2, tmp, !i0&&!i1)
97 ADC (i3, tmp, !i0&&!i1&&!i2)
dd7bbc4a 98 #undef tmp
fe9a76e4 99 }
61fab018 100}
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