new version
[Chiptunes.git] / foo.c
CommitLineData
61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
06aad1ff
TG
10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
3b86ca43
TG
14u8 x;
15u8 t;
16u8 o;
49137fbf 17u8 _;
e98ab46f 18#define Mh o //mod3 vars
dbf91c38 19#define Ml t // -"-
e98ab46f 20//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
8d8c00e4
TG
21void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
5b1c6cc5
TG
24 ADD (Ml, Mh)
25 CLR (Mh)
3d517d8a
TG
26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
0e3d0279 32 ANDI (Ml, 0x0f)
2a69999d 33 ADD (Ml, tmp)
0fc1d6d3
TG
34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
6c72d3c1 37 ANDI (Ml, 0x03)
2a69999d
TG
38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
c3639d5b
TG
44 CPI (Ml, 3)
45 BRPL (skip)
197a5418 46 SUBI (Ml, 3)
c3639d5b 47 skip:;
4283632d 48 RET
8d8c00e4 49 #undef tmp
e98ab46f 50}
965274e2 51void g(void) {
46a8d83c 52 // g(i, x, t, o) -> t
49137fbf 53 #define tmp _
0f219114 54 ANDI (t, 0x07)
32632e61 55 MOV (tmp, i2)
63363195 56 ANDI (tmp, 3)
09cf3949 57 TST (tmp)
49137fbf 58 #undef tmp
09cf3949
TG
59 BREQ (skip)
60 SUBI (t, -8)
61 skip:
c616f0c2 62 t = data[t];
49137fbf
TG
63 /*MOV X_hi==_, data_hi
64 MOV X_lo==t, data_lo
65 ADD X_lo, t
49137fbf
TG
66 ADC X_hi, zero
67 LD t, X */
e5715654
TG
68 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
69 t >>= o; //NOTE: o == {1, 2, 4}
c616f0c2
TG
70 AND (t, x)
71 ANDI (t, 3)
4283632d 72 RET //TODO: CALL/RET is expensive; store PC in register and RJMP, then JRMP back
61fab018
TG
73};
74
75int main(void) {
a1631438
TG
76 u8 n;
77 u8 s;
ab6fe4c2 78 u8 acc;
89f35588 79 //TODO: clear all vars/registers
5dd8b8ff 80 for (;;) {
7874ed03
TG
81 MOV (n, i2)
82 LSL (n)
83 LSL (n)
bc7680e3
TG
84 #define tmp acc
85 MOV (tmp, i1)
5d4207f9
TG
86 SWAP (tmp)
87 ANDI (tmp, 0x0f)
3eef1ade
TG
88 LSR (tmp)
89 LSR (tmp)
128ff01a 90 OR (n, tmp)
bc7680e3 91 #undef tmp
df192822 92 MOV (s, i3)
27b03017
TG
93 ROR (s)
94 ROR (s)
95 ANDI (s, 0x80)
a582bbc3
TG
96 #define tmp acc
97 MOV (tmp, i2)
98 LSR (tmp)
e389879f 99 OR (s, tmp)
df192822 100 #undef tmp
3b86ca43
TG
101
102 //voice 1:
103 LDI (x, 1)
104 MOV (t, n)
9401049b 105 LDI (o, 4)
965274e2 106 RCALL g();
46a8d83c 107 MOV (acc, t)
3b86ca43
TG
108
109 //voice 2:
110 MOV (x, s)
1b023e92 111 #define tmp o
94c4920f
TG
112 MOV (tmp, i2)
113 LSL (tmp)
114 LSL (tmp)
115 LSL (tmp)
116 MOV (t, i1)
4b0b7dc5
TG
117 SWAP (t)
118 ANDI (t, 0xf)
119 LSR (t)
94c4920f 120 OR (t, tmp)
1b023e92 121 #undef tmp
23872091 122 EOR (t, n)
9401049b 123 LDI (o, 2)
965274e2 124 RCALL g();
46a8d83c 125 ADD (acc, t)
3b86ca43
TG
126
127 //voice 3:
2666c079
TG
128 MOV (x, s)
129 INC (x)
17c5b4e9 130 #define tmp o
a7a7abba 131 MOV (tmp, x)
f84bcb7f 132 LSR (tmp)
546b5bab
TG
133 LSR (tmp)
134 ADD (tmp, x)
135 ROR (tmp)
546b5bab
TG
136 LSR (tmp)
137 ADD (tmp, x)
138 ROR (tmp)
546b5bab
TG
139 LSR (tmp)
140 ADD (tmp, x)
141 ROR (tmp)
546b5bab 142 LSR (tmp)
2c94c801 143 MOV (x, tmp)
17c5b4e9 144 #undef tmp
500692e4
TG
145 MOV (Ml, i2)
146 SWAP (Ml)
147 ANDI (Ml, 0xf0)
148 LSL (Ml)
149 #define tmp Mh
150 MOV (tmp, i1)
151 LSR (tmp)
152 LSR (tmp)
153 LSR (tmp)
154 OR (Ml, tmp)
155 #undef tmp
d39a46f5
TG
156 MOV (Mh, i3)
157 SWAP (Mh)
158 ANDI (Mh, 0xf0)
159 LSL (Mh)
160 #define tmp _
161 MOV (tmp, i2)
162 LSR (tmp)
163 LSR (tmp)
164 LSR (tmp)
165 OR (Mh, tmp)
166 #undef tmp
dbf91c38 167 RCALL mod3();
18570947 168 ADD (t, n)
9401049b 169 LDI (o, 2)
965274e2 170 RCALL g();
46a8d83c 171 ADD (acc, t)
3b86ca43
TG
172
173 //voice 4:
6bc3ca83
TG
174 MOV (x, s)
175 INC (x)
176 #define tmp o
86f35aa4
TG
177 MOV (tmp, x)
178 LSR (tmp)
179 ADD (tmp, x)
180 ROR (tmp)
86f35aa4 181 LSR (tmp)
86f35aa4
TG
182 LSR (tmp)
183 ADD (tmp, x)
184 ROR (tmp)
185 ADD (tmp, x)
186 ROR (tmp)
86f35aa4 187 LSR (tmp)
86f35aa4 188 LSR (tmp)
c2693411 189 MOV (x, tmp)
6bc3ca83 190 #undef tmp
649bb224
TG
191 MOV (Ml, i2)
192 SWAP (Ml)
193 ANDI (Ml, 0xf0)
194 LSL (Ml)
195 LSL (Ml)
196 #define tmp Mh
197 MOV (tmp, i1)
198 LSR (tmp)
199 LSR (tmp)
200 OR (Ml, tmp)
201 #undef tmp
18426c43
TG
202 MOV (Mh, i3)
203 SWAP (Mh)
204 ANDI (Mh, 0xf0)
205 LSL (Mh)
206 LSL (Mh)
207 #define tmp _
208 MOV (tmp, i2)
209 LSR (tmp)
210 LSR (tmp)
211 OR (Mh, tmp)
212 #undef tmp
dbf91c38 213 RCALL mod3();
e4f7baf0
TG
214 SUB (t, n)
215 NEG (t)
902cfdea 216 SUBI (t, -8)
9401049b 217 LDI (o, 1)
965274e2 218 RCALL g();
46a8d83c 219 ADD (acc, t)
bfce2f8c 220
95fa231f 221 putchar(acc<<4); //TODO
89f35588 222 SUBI (i0, -1)
95fa231f
TG
223 ADC (i1, zero, !i0)
224 ADC (i2, zero, !i0&&!i1)
225 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 226 }
61fab018 227}
Imprint / Impressum