Commit | Line | Data |
---|---|---|
61fab018 | 1 | #include <stdio.h> |
da32ed67 | 2 | #include "fakeasm.h" |
61fab018 | 3 | typedef unsigned char u8; |
da32ed67 | 4 | |
24abdcbb TG |
5 | u8 data[] = { |
6 | 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58, | |
7 | 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58 | |
8 | }; | |
49137fbf | 9 | u8 zero; |
06aad1ff TG |
10 | u8 i0; |
11 | u8 i1; | |
12 | u8 i2; | |
13 | u8 i3; | |
3b86ca43 TG |
14 | u8 x; |
15 | u8 t; | |
16 | u8 o; | |
49137fbf | 17 | u8 _; |
965274e2 | 18 | void g(void) { |
46a8d83c | 19 | // g(i, x, t, o) -> t |
49137fbf | 20 | #define tmp _ |
0f219114 | 21 | ANDI (t, 0x07) |
32632e61 | 22 | MOV (tmp, i2) |
63363195 | 23 | ANDI (tmp, 3) |
09cf3949 | 24 | TST (tmp) |
49137fbf | 25 | #undef tmp |
09cf3949 TG |
26 | BREQ (skip) |
27 | SUBI (t, -8) | |
28 | skip: | |
c616f0c2 | 29 | t = data[t]; |
49137fbf TG |
30 | /*MOV X_hi==_, data_hi |
31 | MOV X_lo==t, data_lo | |
32 | ADD X_lo, t | |
33 | CLR zero | |
34 | ADC X_hi, zero | |
35 | LD t, X */ | |
36 | t = (((i1&0x1f)<<8|i0)*t)>>8 >> o; //TODO; NOTE: o == {1, 2, 4} | |
c616f0c2 TG |
37 | AND (t, x) |
38 | ANDI (t, 3) | |
46a8d83c | 39 | RET |
61fab018 TG |
40 | }; |
41 | ||
42 | int main(void) { | |
a1631438 TG |
43 | u8 n; |
44 | u8 s; | |
ab6fe4c2 | 45 | u8 acc; |
89f35588 | 46 | //TODO: clear all vars/registers |
5dd8b8ff | 47 | for (;;) { |
7874ed03 TG |
48 | MOV (n, i2) |
49 | LSL (n) | |
50 | LSL (n) | |
bc7680e3 TG |
51 | #define tmp acc |
52 | MOV (tmp, i1) | |
5d4207f9 TG |
53 | SWAP (tmp) |
54 | ANDI (tmp, 0x0f) | |
3eef1ade TG |
55 | LSR (tmp) |
56 | LSR (tmp) | |
128ff01a | 57 | OR (n, tmp) |
bc7680e3 | 58 | #undef tmp |
df192822 | 59 | MOV (s, i3) |
27b03017 TG |
60 | ROR (s) |
61 | ROR (s) | |
62 | ANDI (s, 0x80) | |
a582bbc3 TG |
63 | #define tmp acc |
64 | MOV (tmp, i2) | |
65 | LSR (tmp) | |
e389879f | 66 | OR (s, tmp) |
df192822 | 67 | #undef tmp |
3b86ca43 TG |
68 | |
69 | //voice 1: | |
70 | LDI (x, 1) | |
71 | MOV (t, n) | |
9401049b | 72 | LDI (o, 4) |
965274e2 | 73 | RCALL g(); |
46a8d83c | 74 | MOV (acc, t) |
3b86ca43 TG |
75 | |
76 | //voice 2: | |
77 | MOV (x, s) | |
1b023e92 | 78 | #define tmp o |
94c4920f TG |
79 | MOV (tmp, i2) |
80 | LSL (tmp) | |
81 | LSL (tmp) | |
82 | LSL (tmp) | |
83 | MOV (t, i1) | |
4b0b7dc5 TG |
84 | SWAP (t) |
85 | ANDI (t, 0xf) | |
86 | LSR (t) | |
94c4920f | 87 | OR (t, tmp) |
1b023e92 | 88 | #undef tmp |
23872091 | 89 | EOR (t, n) |
9401049b | 90 | LDI (o, 2) |
965274e2 | 91 | RCALL g(); |
46a8d83c | 92 | ADD (acc, t) |
3b86ca43 TG |
93 | |
94 | //voice 3: | |
2666c079 TG |
95 | MOV (x, s) |
96 | INC (x) | |
17c5b4e9 | 97 | #define tmp o |
a7a7abba | 98 | MOV (tmp, x) |
f84bcb7f | 99 | LSR (tmp) |
546b5bab TG |
100 | LSR (tmp) |
101 | ADD (tmp, x) | |
102 | ROR (tmp) | |
546b5bab TG |
103 | LSR (tmp) |
104 | ADD (tmp, x) | |
105 | ROR (tmp) | |
546b5bab TG |
106 | LSR (tmp) |
107 | ADD (tmp, x) | |
108 | ROR (tmp) | |
546b5bab | 109 | LSR (tmp) |
2c94c801 | 110 | MOV (x, tmp) |
17c5b4e9 | 111 | #undef tmp |
49137fbf | 112 | t = ((i3&0x01)<<13 | i2<<5 | i1>>3) % 3; //TODO |
18570947 | 113 | ADD (t, n) |
9401049b | 114 | LDI (o, 2) |
965274e2 | 115 | RCALL g(); |
46a8d83c | 116 | ADD (acc, t) |
3b86ca43 TG |
117 | |
118 | //voice 4: | |
6bc3ca83 TG |
119 | MOV (x, s) |
120 | INC (x) | |
121 | #define tmp o | |
86f35aa4 TG |
122 | MOV (tmp, x) |
123 | LSR (tmp) | |
124 | ADD (tmp, x) | |
125 | ROR (tmp) | |
86f35aa4 | 126 | LSR (tmp) |
86f35aa4 TG |
127 | LSR (tmp) |
128 | ADD (tmp, x) | |
129 | ROR (tmp) | |
130 | ADD (tmp, x) | |
131 | ROR (tmp) | |
86f35aa4 | 132 | LSR (tmp) |
86f35aa4 | 133 | LSR (tmp) |
c2693411 | 134 | MOV (x, tmp) |
6bc3ca83 | 135 | #undef tmp |
49137fbf | 136 | t = ((i3&0x01)<<14 | i2<<6 | i1>>2) % 3; //TODO |
e4f7baf0 TG |
137 | SUB (t, n) |
138 | NEG (t) | |
902cfdea | 139 | SUBI (t, -8) |
9401049b | 140 | LDI (o, 1) |
965274e2 | 141 | RCALL g(); |
46a8d83c | 142 | ADD (acc, t) |
bfce2f8c | 143 | |
ab6fe4c2 | 144 | putchar(acc<<4); |
89f35588 | 145 | #define tmp acc |
3df69ede | 146 | CLR (tmp) //NOTE: maybe use dedicated zero register? |
89f35588 TG |
147 | SUBI (i0, -1) |
148 | ADC (i1, tmp, !i0) | |
149 | ADC (i2, tmp, !i0&&!i1) | |
150 | ADC (i3, tmp, !i0&&!i1&&!i2) | |
dd7bbc4a | 151 | #undef tmp |
fe9a76e4 | 152 | } |
61fab018 | 153 | } |