Commit | Line | Data |
---|---|---|
61fab018 | 1 | #include <stdio.h> |
da32ed67 | 2 | #include "fakeasm.h" |
61fab018 | 3 | typedef unsigned char u8; |
da32ed67 | 4 | |
24abdcbb TG |
5 | u8 data[] = { |
6 | 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58, | |
7 | 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58 | |
8 | }; | |
61592bdd TG |
9 | u8 zero; //r16 |
10 | u8 acc; //r17 | |
11 | u8 i0; //r18 | |
12 | u8 i1; //r19 | |
13 | u8 i2; //r20 | |
14 | u8 i3; //r21 | |
15 | u8 n; //r22 | |
16 | u8 s; //r23 | |
17 | u8 _; //r24 | |
18 | //r25 | |
19 | u8 t;/*==Ml*/ //r26 (Xlo) | |
20 | u8 x;/*==Mh*/ //r27 (Xhi) | |
21 | //r28 | |
22 | //r29 | |
23 | /*fakestack_l*/ //r30 (Zlo) | |
24 | /*fakestack_h*/ //r31 (Zhi) | |
37bf20ea | 25 | #define Mh x //mod3 vars |
dbf91c38 | 26 | #define Ml t // -"- |
e98ab46f | 27 | //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml |
8d8c00e4 TG |
28 | void mod3(void) { |
29 | // mod3(Mh.Ml) -> t | |
30 | #define tmp _ | |
5b1c6cc5 TG |
31 | ADD (Ml, Mh) |
32 | CLR (Mh) | |
3d517d8a TG |
33 | ADC (Mh, zero, carry) //Mh only holds the carry bit |
34 | MOV (tmp, Ml) | |
35 | SWAP (tmp) | |
36 | ANDI (tmp, 0x0f) | |
37 | SWAP (Mh) | |
38 | OR (tmp, Mh) | |
0e3d0279 | 39 | ANDI (Ml, 0x0f) |
2a69999d | 40 | ADD (Ml, tmp) |
0fc1d6d3 TG |
41 | MOV (tmp, Ml) |
42 | LSR (tmp) | |
43 | LSR (tmp) | |
6c72d3c1 | 44 | ANDI (Ml, 0x03) |
2a69999d TG |
45 | ADD (Ml, tmp) |
46 | MOV (tmp, Ml) | |
47 | LSR (tmp) | |
48 | LSR (tmp) | |
49 | ANDI (Ml, 0x03) | |
50 | ADD (Ml, tmp) | |
c3639d5b TG |
51 | CPI (Ml, 3) |
52 | BRPL (skip) | |
197a5418 | 53 | SUBI (Ml, 3) |
c3639d5b | 54 | skip:; |
4283632d | 55 | RET |
8d8c00e4 | 56 | #undef tmp |
e98ab46f | 57 | } |
965274e2 | 58 | void g(void) { |
362b33c9 | 59 | // g(i, t) -> t |
eafeaf93 | 60 | // tempvars: `x` and `_` |
49137fbf | 61 | #define tmp _ |
0f219114 | 62 | ANDI (t, 0x07) |
32632e61 | 63 | MOV (tmp, i2) |
63363195 | 64 | ANDI (tmp, 3) |
09cf3949 | 65 | TST (tmp) |
49137fbf | 66 | #undef tmp |
09cf3949 TG |
67 | BREQ (skip) |
68 | SUBI (t, -8) | |
69 | skip: | |
c616f0c2 | 70 | t = data[t]; |
8ee3310e | 71 | /*MOV X_hi==x, data_hi |
49137fbf TG |
72 | MOV X_lo==t, data_lo |
73 | ADD X_lo, t | |
49137fbf TG |
74 | ADC X_hi, zero |
75 | LD t, X */ | |
d46aea64 | 76 | t &= 0xfd; //hint |
e5715654 | 77 | t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO |
d46aea64 | 78 | t &= 0x1e; //hint |
d5b74a12 | 79 | RET //TODO: replace CALL/RET with IJMP? |
61fab018 TG |
80 | }; |
81 | ||
82 | int main(void) { | |
23e66ca4 TG |
83 | CLR (zero) |
84 | CLR (i0) | |
85 | CLR (i1) | |
86 | CLR (i2) | |
87 | CLR (i3) | |
5dd8b8ff | 88 | for (;;) { |
7874ed03 TG |
89 | MOV (n, i2) |
90 | LSL (n) | |
91 | LSL (n) | |
8ee3310e | 92 | #define tmp _ |
bc7680e3 | 93 | MOV (tmp, i1) |
5d4207f9 TG |
94 | SWAP (tmp) |
95 | ANDI (tmp, 0x0f) | |
3eef1ade TG |
96 | LSR (tmp) |
97 | LSR (tmp) | |
128ff01a | 98 | OR (n, tmp) |
bc7680e3 | 99 | #undef tmp |
df192822 | 100 | MOV (s, i3) |
27b03017 TG |
101 | ROR (s) |
102 | ROR (s) | |
103 | ANDI (s, 0x80) | |
8ee3310e | 104 | #define tmp _ |
a582bbc3 TG |
105 | MOV (tmp, i2) |
106 | LSR (tmp) | |
e389879f | 107 | OR (s, tmp) |
df192822 | 108 | #undef tmp |
3b86ca43 TG |
109 | |
110 | //voice 1: | |
3b86ca43 | 111 | MOV (t, n) |
965274e2 | 112 | RCALL g(); |
c09a6ed8 | 113 | SWAP (t) |
4b21c1a7 | 114 | //ANDI (t, 1) |
46a8d83c | 115 | MOV (acc, t) |
3b86ca43 TG |
116 | |
117 | //voice 2: | |
37bf20ea | 118 | #define tmp _ |
94c4920f TG |
119 | MOV (tmp, i2) |
120 | LSL (tmp) | |
121 | LSL (tmp) | |
122 | LSL (tmp) | |
123 | MOV (t, i1) | |
4b0b7dc5 TG |
124 | SWAP (t) |
125 | ANDI (t, 0xf) | |
126 | LSR (t) | |
94c4920f | 127 | OR (t, tmp) |
1b023e92 | 128 | #undef tmp |
23872091 | 129 | EOR (t, n) |
965274e2 | 130 | RCALL g(); |
7716b427 TG |
131 | LSR (t) |
132 | LSR (t) | |
133 | ANDI (t, 3) | |
f28def6a | 134 | AND (t, s) |
46a8d83c | 135 | ADD (acc, t) |
3b86ca43 TG |
136 | |
137 | //voice 3: | |
500692e4 TG |
138 | MOV (Ml, i2) |
139 | SWAP (Ml) | |
140 | ANDI (Ml, 0xf0) | |
141 | LSL (Ml) | |
8ee3310e | 142 | #define tmp _ |
500692e4 TG |
143 | MOV (tmp, i1) |
144 | LSR (tmp) | |
145 | LSR (tmp) | |
146 | LSR (tmp) | |
147 | OR (Ml, tmp) | |
148 | #undef tmp | |
d39a46f5 TG |
149 | MOV (Mh, i3) |
150 | SWAP (Mh) | |
151 | ANDI (Mh, 0xf0) | |
152 | LSL (Mh) | |
153 | #define tmp _ | |
154 | MOV (tmp, i2) | |
155 | LSR (tmp) | |
156 | LSR (tmp) | |
157 | LSR (tmp) | |
158 | OR (Mh, tmp) | |
159 | #undef tmp | |
dbf91c38 | 160 | RCALL mod3(); |
18570947 | 161 | ADD (t, n) |
965274e2 | 162 | RCALL g(); |
c6c6cbe5 TG |
163 | LSR (t) |
164 | LSR (t) | |
165 | ANDI (t, 3) | |
f28def6a TG |
166 | MOV (x, s) |
167 | INC (x) | |
37bf20ea | 168 | #define tmp _ |
f28def6a TG |
169 | MOV (tmp, x) |
170 | LSR (tmp) | |
171 | LSR (tmp) | |
172 | ADD (tmp, x) | |
173 | ROR (tmp) | |
174 | LSR (tmp) | |
175 | ADD (tmp, x) | |
176 | ROR (tmp) | |
177 | LSR (tmp) | |
178 | ADD (tmp, x) | |
179 | ROR (tmp) | |
180 | LSR (tmp) | |
181 | MOV (x, tmp) | |
182 | #undef tmp | |
5d9a2389 | 183 | AND (t, x) |
46a8d83c | 184 | ADD (acc, t) |
3b86ca43 TG |
185 | |
186 | //voice 4: | |
649bb224 TG |
187 | MOV (Ml, i2) |
188 | SWAP (Ml) | |
189 | ANDI (Ml, 0xf0) | |
190 | LSL (Ml) | |
191 | LSL (Ml) | |
8ee3310e | 192 | #define tmp _ |
649bb224 TG |
193 | MOV (tmp, i1) |
194 | LSR (tmp) | |
195 | LSR (tmp) | |
196 | OR (Ml, tmp) | |
197 | #undef tmp | |
18426c43 TG |
198 | MOV (Mh, i3) |
199 | SWAP (Mh) | |
200 | ANDI (Mh, 0xf0) | |
201 | LSL (Mh) | |
202 | LSL (Mh) | |
203 | #define tmp _ | |
204 | MOV (tmp, i2) | |
205 | LSR (tmp) | |
206 | LSR (tmp) | |
207 | OR (Mh, tmp) | |
208 | #undef tmp | |
dbf91c38 | 209 | RCALL mod3(); |
e4f7baf0 TG |
210 | SUB (t, n) |
211 | NEG (t) | |
902cfdea | 212 | SUBI (t, -8) |
965274e2 | 213 | RCALL g(); |
c6c6cbe5 TG |
214 | LSR (t) |
215 | ANDI (t, 3) | |
d8af0686 TG |
216 | MOV (x, s) |
217 | INC (x) | |
37bf20ea | 218 | #define tmp _ |
d8af0686 TG |
219 | MOV (tmp, x) |
220 | LSR (tmp) | |
221 | ADD (tmp, x) | |
222 | ROR (tmp) | |
223 | LSR (tmp) | |
224 | LSR (tmp) | |
225 | ADD (tmp, x) | |
226 | ROR (tmp) | |
227 | ADD (tmp, x) | |
228 | ROR (tmp) | |
229 | LSR (tmp) | |
230 | LSR (tmp) | |
231 | MOV (x, tmp) | |
232 | #undef tmp | |
5d9a2389 | 233 | AND (t, x) |
46a8d83c | 234 | ADD (acc, t) |
bfce2f8c | 235 | |
95fa231f | 236 | putchar(acc<<4); //TODO |
89f35588 | 237 | SUBI (i0, -1) |
95fa231f TG |
238 | ADC (i1, zero, !i0) |
239 | ADC (i2, zero, !i0&&!i1) | |
240 | ADC (i3, zero, !i0&&!i1&&!i2) | |
fe9a76e4 | 241 | } |
61fab018 | 242 | } |