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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
61592bdd
TG
9u8 zero; //r16
10u8 acc; //r17
11u8 i0; //r18
12u8 i1; //r19
13u8 i2; //r20
14u8 i3; //r21
15u8 n; //r22
16u8 s; //r23
17u8 _; //r24
18 //r25
19u8 t;/*==Ml*/ //r26 (Xlo)
20u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23/*fakestack_l*/ //r30 (Zlo)
24/*fakestack_h*/ //r31 (Zhi)
37bf20ea 25#define Mh x //mod3 vars
dbf91c38 26#define Ml t // -"-
e98ab46f 27//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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28void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
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31 ADD (Ml, Mh)
32 CLR (Mh)
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33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
0e3d0279 39 ANDI (Ml, 0x0f)
2a69999d 40 ADD (Ml, tmp)
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41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
6c72d3c1 44 ANDI (Ml, 0x03)
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45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
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51 CPI (Ml, 3)
52 BRPL (skip)
197a5418 53 SUBI (Ml, 3)
c3639d5b 54 skip:;
4283632d 55 RET
8d8c00e4 56 #undef tmp
e98ab46f 57}
965274e2 58void g(void) {
362b33c9 59 // g(i, t) -> t
eafeaf93 60 // tempvars: `x` and `_`
49137fbf 61 #define tmp _
0f219114 62 ANDI (t, 0x07)
32632e61 63 MOV (tmp, i2)
63363195 64 ANDI (tmp, 3)
09cf3949 65 TST (tmp)
49137fbf 66 #undef tmp
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67 BREQ (skip)
68 SUBI (t, -8)
69 skip:
c616f0c2 70 t = data[t];
8ee3310e 71 /*MOV X_hi==x, data_hi
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72 MOV X_lo==t, data_lo
73 ADD X_lo, t
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74 ADC X_hi, zero
75 LD t, X */
d46aea64 76 t &= 0xfd; //hint
e5715654 77 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
d46aea64 78 t &= 0x1e; //hint
d5b74a12 79 RET //TODO: replace CALL/RET with IJMP?
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80};
81
82int main(void) {
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83 CLR (zero)
84 CLR (i0)
85 CLR (i1)
86 CLR (i2)
87 CLR (i3)
5dd8b8ff 88 for (;;) {
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89 MOV (n, i2)
90 LSL (n)
91 LSL (n)
8ee3310e 92 #define tmp _
bc7680e3 93 MOV (tmp, i1)
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94 SWAP (tmp)
95 ANDI (tmp, 0x0f)
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96 LSR (tmp)
97 LSR (tmp)
128ff01a 98 OR (n, tmp)
bc7680e3 99 #undef tmp
df192822 100 MOV (s, i3)
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101 ROR (s)
102 ROR (s)
103 ANDI (s, 0x80)
8ee3310e 104 #define tmp _
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105 MOV (tmp, i2)
106 LSR (tmp)
e389879f 107 OR (s, tmp)
df192822 108 #undef tmp
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109
110 //voice 1:
3b86ca43 111 MOV (t, n)
965274e2 112 RCALL g();
c09a6ed8 113 SWAP (t)
4b21c1a7 114 //ANDI (t, 1)
46a8d83c 115 MOV (acc, t)
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116
117 //voice 2:
37bf20ea 118 #define tmp _
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119 MOV (tmp, i2)
120 LSL (tmp)
121 LSL (tmp)
122 LSL (tmp)
123 MOV (t, i1)
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124 SWAP (t)
125 ANDI (t, 0xf)
126 LSR (t)
94c4920f 127 OR (t, tmp)
1b023e92 128 #undef tmp
23872091 129 EOR (t, n)
965274e2 130 RCALL g();
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131 LSR (t)
132 LSR (t)
133 ANDI (t, 3)
f28def6a 134 AND (t, s)
46a8d83c 135 ADD (acc, t)
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136
137 //voice 3:
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138 MOV (Ml, i2)
139 SWAP (Ml)
140 ANDI (Ml, 0xf0)
141 LSL (Ml)
8ee3310e 142 #define tmp _
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143 MOV (tmp, i1)
144 LSR (tmp)
145 LSR (tmp)
146 LSR (tmp)
147 OR (Ml, tmp)
148 #undef tmp
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149 MOV (Mh, i3)
150 SWAP (Mh)
151 ANDI (Mh, 0xf0)
152 LSL (Mh)
153 #define tmp _
154 MOV (tmp, i2)
155 LSR (tmp)
156 LSR (tmp)
157 LSR (tmp)
158 OR (Mh, tmp)
159 #undef tmp
dbf91c38 160 RCALL mod3();
18570947 161 ADD (t, n)
965274e2 162 RCALL g();
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163 LSR (t)
164 LSR (t)
165 ANDI (t, 3)
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166 MOV (x, s)
167 INC (x)
37bf20ea 168 #define tmp _
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169 MOV (tmp, x)
170 LSR (tmp)
171 LSR (tmp)
172 ADD (tmp, x)
173 ROR (tmp)
174 LSR (tmp)
175 ADD (tmp, x)
176 ROR (tmp)
177 LSR (tmp)
178 ADD (tmp, x)
179 ROR (tmp)
180 LSR (tmp)
181 MOV (x, tmp)
182 #undef tmp
5d9a2389 183 AND (t, x)
46a8d83c 184 ADD (acc, t)
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185
186 //voice 4:
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187 MOV (Ml, i2)
188 SWAP (Ml)
189 ANDI (Ml, 0xf0)
190 LSL (Ml)
191 LSL (Ml)
8ee3310e 192 #define tmp _
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193 MOV (tmp, i1)
194 LSR (tmp)
195 LSR (tmp)
196 OR (Ml, tmp)
197 #undef tmp
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198 MOV (Mh, i3)
199 SWAP (Mh)
200 ANDI (Mh, 0xf0)
201 LSL (Mh)
202 LSL (Mh)
203 #define tmp _
204 MOV (tmp, i2)
205 LSR (tmp)
206 LSR (tmp)
207 OR (Mh, tmp)
208 #undef tmp
dbf91c38 209 RCALL mod3();
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210 SUB (t, n)
211 NEG (t)
902cfdea 212 SUBI (t, -8)
965274e2 213 RCALL g();
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214 LSR (t)
215 ANDI (t, 3)
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216 MOV (x, s)
217 INC (x)
37bf20ea 218 #define tmp _
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219 MOV (tmp, x)
220 LSR (tmp)
221 ADD (tmp, x)
222 ROR (tmp)
223 LSR (tmp)
224 LSR (tmp)
225 ADD (tmp, x)
226 ROR (tmp)
227 ADD (tmp, x)
228 ROR (tmp)
229 LSR (tmp)
230 LSR (tmp)
231 MOV (x, tmp)
232 #undef tmp
5d9a2389 233 AND (t, x)
46a8d83c 234 ADD (acc, t)
bfce2f8c 235
95fa231f 236 putchar(acc<<4); //TODO
89f35588 237 SUBI (i0, -1)
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TG
238 ADC (i1, zero, !i0)
239 ADC (i2, zero, !i0&&!i1)
240 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 241 }
61fab018 242}
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