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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
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10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
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14u8 x;
15u8 t;
16u8 o;
49137fbf 17u8 _;
e98ab46f 18#define Mh o //mod3 vars
dbf91c38 19#define Ml t // -"-
e98ab46f 20//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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21void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
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24 ADD (Ml, Mh)
25 CLR (Mh)
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26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
0e3d0279 32 ANDI (Ml, 0x0f)
2a69999d 33 ADD (Ml, tmp)
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34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
6c72d3c1 37 ANDI (Ml, 0x03)
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38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
c3639d5b
TG
44 CPI (Ml, 3)
45 BRPL (skip)
197a5418 46 SUBI (Ml, 3)
c3639d5b 47 skip:;
8d8c00e4 48 #undef tmp
e98ab46f 49}
965274e2 50void g(void) {
46a8d83c 51 // g(i, x, t, o) -> t
49137fbf 52 #define tmp _
0f219114 53 ANDI (t, 0x07)
32632e61 54 MOV (tmp, i2)
63363195 55 ANDI (tmp, 3)
09cf3949 56 TST (tmp)
49137fbf 57 #undef tmp
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58 BREQ (skip)
59 SUBI (t, -8)
60 skip:
c616f0c2 61 t = data[t];
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62 /*MOV X_hi==_, data_hi
63 MOV X_lo==t, data_lo
64 ADD X_lo, t
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65 ADC X_hi, zero
66 LD t, X */
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67 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
68 t >>= o; //NOTE: o == {1, 2, 4}
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69 AND (t, x)
70 ANDI (t, 3)
46a8d83c 71 RET
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72};
73
74int main(void) {
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75 u8 n;
76 u8 s;
ab6fe4c2 77 u8 acc;
89f35588 78 //TODO: clear all vars/registers
5dd8b8ff 79 for (;;) {
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80 MOV (n, i2)
81 LSL (n)
82 LSL (n)
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83 #define tmp acc
84 MOV (tmp, i1)
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85 SWAP (tmp)
86 ANDI (tmp, 0x0f)
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87 LSR (tmp)
88 LSR (tmp)
128ff01a 89 OR (n, tmp)
bc7680e3 90 #undef tmp
df192822 91 MOV (s, i3)
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92 ROR (s)
93 ROR (s)
94 ANDI (s, 0x80)
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95 #define tmp acc
96 MOV (tmp, i2)
97 LSR (tmp)
e389879f 98 OR (s, tmp)
df192822 99 #undef tmp
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100
101 //voice 1:
102 LDI (x, 1)
103 MOV (t, n)
9401049b 104 LDI (o, 4)
965274e2 105 RCALL g();
46a8d83c 106 MOV (acc, t)
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107
108 //voice 2:
109 MOV (x, s)
1b023e92 110 #define tmp o
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111 MOV (tmp, i2)
112 LSL (tmp)
113 LSL (tmp)
114 LSL (tmp)
115 MOV (t, i1)
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116 SWAP (t)
117 ANDI (t, 0xf)
118 LSR (t)
94c4920f 119 OR (t, tmp)
1b023e92 120 #undef tmp
23872091 121 EOR (t, n)
9401049b 122 LDI (o, 2)
965274e2 123 RCALL g();
46a8d83c 124 ADD (acc, t)
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125
126 //voice 3:
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127 MOV (x, s)
128 INC (x)
17c5b4e9 129 #define tmp o
a7a7abba 130 MOV (tmp, x)
f84bcb7f 131 LSR (tmp)
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132 LSR (tmp)
133 ADD (tmp, x)
134 ROR (tmp)
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135 LSR (tmp)
136 ADD (tmp, x)
137 ROR (tmp)
546b5bab
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138 LSR (tmp)
139 ADD (tmp, x)
140 ROR (tmp)
546b5bab 141 LSR (tmp)
2c94c801 142 MOV (x, tmp)
17c5b4e9 143 #undef tmp
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144 MOV (Ml, i2)
145 SWAP (Ml)
146 ANDI (Ml, 0xf0)
147 LSL (Ml)
148 #define tmp Mh
149 MOV (tmp, i1)
150 LSR (tmp)
151 LSR (tmp)
152 LSR (tmp)
153 OR (Ml, tmp)
154 #undef tmp
e98ab46f 155 Mh = i3<<5 | i2>>3;
dbf91c38 156 RCALL mod3();
18570947 157 ADD (t, n)
9401049b 158 LDI (o, 2)
965274e2 159 RCALL g();
46a8d83c 160 ADD (acc, t)
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161
162 //voice 4:
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163 MOV (x, s)
164 INC (x)
165 #define tmp o
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166 MOV (tmp, x)
167 LSR (tmp)
168 ADD (tmp, x)
169 ROR (tmp)
86f35aa4 170 LSR (tmp)
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171 LSR (tmp)
172 ADD (tmp, x)
173 ROR (tmp)
174 ADD (tmp, x)
175 ROR (tmp)
86f35aa4 176 LSR (tmp)
86f35aa4 177 LSR (tmp)
c2693411 178 MOV (x, tmp)
6bc3ca83 179 #undef tmp
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180 Ml = i2<<6 | i1>>2;
181 Mh = i3<<6 | i2>>2;
dbf91c38 182 RCALL mod3();
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183 SUB (t, n)
184 NEG (t)
902cfdea 185 SUBI (t, -8)
9401049b 186 LDI (o, 1)
965274e2 187 RCALL g();
46a8d83c 188 ADD (acc, t)
bfce2f8c 189
95fa231f 190 putchar(acc<<4); //TODO
89f35588 191 SUBI (i0, -1)
95fa231f
TG
192 ADC (i1, zero, !i0)
193 ADC (i2, zero, !i0&&!i1)
194 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 195 }
61fab018 196}
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