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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
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5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
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9u8 zero; //r16
10u8 acc; //r17
11u8 i0; //r18
12u8 i1; //r19
13u8 i2; //r20
14u8 i3; //r21
15u8 n; //r22
16u8 s; //r23
17u8 _; //r24
18 //r25
19u8 t;/*==Ml*/ //r26 (Xlo)
20u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23/*fakestack_l*/ //r30 (Zlo)
24/*fakestack_h*/ //r31 (Zhi)
37bf20ea 25#define Mh x //mod3 vars
dbf91c38 26#define Ml t // -"-
e98ab46f 27//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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28void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
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31 ADD (Ml, Mh)
32 CLR (Mh)
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33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
0e3d0279 39 ANDI (Ml, 0x0f)
2a69999d 40 ADD (Ml, tmp)
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41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
6c72d3c1 44 ANDI (Ml, 0x03)
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45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
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51 CPI (Ml, 3)
52 BRPL (skip)
197a5418 53 SUBI (Ml, 3)
c3639d5b 54 skip:;
4283632d 55 RET
8d8c00e4 56 #undef tmp
e98ab46f 57}
965274e2 58void g(void) {
362b33c9 59 // g(i, t) -> t
eafeaf93 60 // tempvars: `x` and `_`
49137fbf 61 #define tmp _
0f219114 62 ANDI (t, 0x07)
32632e61 63 MOV (tmp, i2)
63363195 64 ANDI (tmp, 3)
09cf3949 65 TST (tmp)
49137fbf 66 #undef tmp
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67 BREQ (skip)
68 SUBI (t, -8)
69 skip:
c616f0c2 70 t = data[t];
8ee3310e 71 /*MOV X_hi==x, data_hi
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72 MOV X_lo==t, data_lo
73 ADD X_lo, t
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74 ADC X_hi, zero
75 LD t, X */
d46aea64 76 t &= 0xfd; //hint
e5715654 77 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
d46aea64 78 t &= 0x1e; //hint
d5b74a12 79 RET //TODO: replace CALL/RET with IJMP?
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80};
81
82int main(void) {
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83 CLR (zero)
84 CLR (i0)
85 CLR (i1)
86 CLR (i2)
87 CLR (i3)
5dd8b8ff 88 for (;;) {
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89 MOV (n, i2)
90 LSL (n)
91 LSL (n)
8ee3310e 92 #define tmp _
bc7680e3 93 MOV (tmp, i1)
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94 SWAP (tmp)
95 ANDI (tmp, 0x0f)
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96 LSR (tmp)
97 LSR (tmp)
128ff01a 98 OR (n, tmp)
bc7680e3 99 #undef tmp
df192822 100 MOV (s, i3)
2bbe001f 101 LSR (s)
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102 ROR (s)
103 ANDI (s, 0x80)
8ee3310e 104 #define tmp _
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105 MOV (tmp, i2)
106 LSR (tmp)
e389879f 107 OR (s, tmp)
df192822 108 #undef tmp
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109
110 //voice 1:
3b86ca43 111 MOV (t, n)
965274e2 112 RCALL g();
c09a6ed8 113 SWAP (t)
46a8d83c 114 MOV (acc, t)
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115
116 //voice 2:
37bf20ea 117 #define tmp _
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118 MOV (tmp, i2)
119 LSL (tmp)
120 LSL (tmp)
121 LSL (tmp)
122 MOV (t, i1)
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123 SWAP (t)
124 ANDI (t, 0xf)
125 LSR (t)
94c4920f 126 OR (t, tmp)
1b023e92 127 #undef tmp
23872091 128 EOR (t, n)
965274e2 129 RCALL g();
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130 LSR (t)
131 LSR (t)
132 ANDI (t, 3)
f28def6a 133 AND (t, s)
46a8d83c 134 ADD (acc, t)
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135
136 //voice 3:
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137 MOV (Ml, i2)
138 SWAP (Ml)
139 ANDI (Ml, 0xf0)
140 LSL (Ml)
8ee3310e 141 #define tmp _
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142 MOV (tmp, i1)
143 LSR (tmp)
144 LSR (tmp)
145 LSR (tmp)
146 OR (Ml, tmp)
147 #undef tmp
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148 MOV (Mh, i3)
149 SWAP (Mh)
150 ANDI (Mh, 0xf0)
151 LSL (Mh)
152 #define tmp _
153 MOV (tmp, i2)
154 LSR (tmp)
155 LSR (tmp)
156 LSR (tmp)
157 OR (Mh, tmp)
158 #undef tmp
dbf91c38 159 RCALL mod3();
18570947 160 ADD (t, n)
965274e2 161 RCALL g();
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162 LSR (t)
163 LSR (t)
164 ANDI (t, 3)
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165 MOV (x, s)
166 INC (x)
37bf20ea 167 #define tmp _
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168 MOV (tmp, x)
169 LSR (tmp)
170 LSR (tmp)
171 ADD (tmp, x)
172 ROR (tmp)
173 LSR (tmp)
174 ADD (tmp, x)
175 ROR (tmp)
176 LSR (tmp)
177 ADD (tmp, x)
178 ROR (tmp)
179 LSR (tmp)
51f43293 180 AND (t, tmp)
f28def6a 181 #undef tmp
46a8d83c 182 ADD (acc, t)
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183
184 //voice 4:
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185 MOV (Ml, i2)
186 SWAP (Ml)
187 ANDI (Ml, 0xf0)
188 LSL (Ml)
189 LSL (Ml)
8ee3310e 190 #define tmp _
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191 MOV (tmp, i1)
192 LSR (tmp)
193 LSR (tmp)
194 OR (Ml, tmp)
195 #undef tmp
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196 MOV (Mh, i3)
197 SWAP (Mh)
198 ANDI (Mh, 0xf0)
199 LSL (Mh)
200 LSL (Mh)
201 #define tmp _
202 MOV (tmp, i2)
203 LSR (tmp)
204 LSR (tmp)
205 OR (Mh, tmp)
206 #undef tmp
dbf91c38 207 RCALL mod3();
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208 SUB (t, n)
209 NEG (t)
902cfdea 210 SUBI (t, -8)
965274e2 211 RCALL g();
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212 LSR (t)
213 ANDI (t, 3)
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214 MOV (x, s)
215 INC (x)
37bf20ea 216 #define tmp _
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217 MOV (tmp, x)
218 LSR (tmp)
219 ADD (tmp, x)
220 ROR (tmp)
221 LSR (tmp)
222 LSR (tmp)
223 ADD (tmp, x)
224 ROR (tmp)
225 ADD (tmp, x)
226 ROR (tmp)
227 LSR (tmp)
228 LSR (tmp)
51f43293 229 AND (t, tmp)
d8af0686 230 #undef tmp
46a8d83c 231 ADD (acc, t)
bfce2f8c 232
95fa231f 233 putchar(acc<<4); //TODO
89f35588 234 SUBI (i0, -1)
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235 ADC (i1, zero, !i0)
236 ADC (i2, zero, !i0&&!i1)
237 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 238 }
61fab018 239}
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