Commit | Line | Data |
---|---|---|
61fab018 | 1 | #include <stdio.h> |
da32ed67 | 2 | #include "fakeasm.h" |
61fab018 | 3 | typedef unsigned char u8; |
da32ed67 | 4 | |
24abdcbb TG |
5 | u8 data[] = { |
6 | 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58, | |
7 | 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58 | |
8 | }; | |
95fa231f | 9 | u8 zero; //zero register |
06aad1ff TG |
10 | u8 i0; |
11 | u8 i1; | |
12 | u8 i2; | |
13 | u8 i3; | |
3b86ca43 TG |
14 | u8 x; |
15 | u8 t; | |
16 | u8 o; | |
49137fbf | 17 | u8 _; |
e98ab46f | 18 | #define Mh o //mod3 vars |
dbf91c38 TG |
19 | #define Ml t // -"- |
20 | void mod3(void) { //avail: t, o _ | |
e98ab46f | 21 | //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml |
5b1c6cc5 TG |
22 | #define tmp _ |
23 | //unsigned short a = ((Mh) + (Ml)) ;//&0x1ff; | |
24 | // Mh = a>>8; //1 bit | |
25 | // Ml = a; | |
26 | ADD (Ml, Mh) | |
27 | CLR (Mh) | |
28 | ADC (Mh, zero, carry) | |
dbf91c38 TG |
29 | Ml = (Mh<<4|Ml>>4) + (Ml & 0xF); |
30 | Ml = (Ml >> 2) + (Ml & 0x3); | |
31 | Ml = (Ml >> 2) + (Ml & 0x3); | |
32 | if (Ml > 2) Ml = Ml - 3; | |
5b1c6cc5 | 33 | #undef tmp |
e98ab46f | 34 | } |
965274e2 | 35 | void g(void) { |
46a8d83c | 36 | // g(i, x, t, o) -> t |
49137fbf | 37 | #define tmp _ |
0f219114 | 38 | ANDI (t, 0x07) |
32632e61 | 39 | MOV (tmp, i2) |
63363195 | 40 | ANDI (tmp, 3) |
09cf3949 | 41 | TST (tmp) |
49137fbf | 42 | #undef tmp |
09cf3949 TG |
43 | BREQ (skip) |
44 | SUBI (t, -8) | |
45 | skip: | |
c616f0c2 | 46 | t = data[t]; |
49137fbf TG |
47 | /*MOV X_hi==_, data_hi |
48 | MOV X_lo==t, data_lo | |
49 | ADD X_lo, t | |
49137fbf TG |
50 | ADC X_hi, zero |
51 | LD t, X */ | |
e5715654 TG |
52 | t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO |
53 | t >>= o; //NOTE: o == {1, 2, 4} | |
c616f0c2 TG |
54 | AND (t, x) |
55 | ANDI (t, 3) | |
46a8d83c | 56 | RET |
61fab018 TG |
57 | }; |
58 | ||
59 | int main(void) { | |
a1631438 TG |
60 | u8 n; |
61 | u8 s; | |
ab6fe4c2 | 62 | u8 acc; |
89f35588 | 63 | //TODO: clear all vars/registers |
5dd8b8ff | 64 | for (;;) { |
7874ed03 TG |
65 | MOV (n, i2) |
66 | LSL (n) | |
67 | LSL (n) | |
bc7680e3 TG |
68 | #define tmp acc |
69 | MOV (tmp, i1) | |
5d4207f9 TG |
70 | SWAP (tmp) |
71 | ANDI (tmp, 0x0f) | |
3eef1ade TG |
72 | LSR (tmp) |
73 | LSR (tmp) | |
128ff01a | 74 | OR (n, tmp) |
bc7680e3 | 75 | #undef tmp |
df192822 | 76 | MOV (s, i3) |
27b03017 TG |
77 | ROR (s) |
78 | ROR (s) | |
79 | ANDI (s, 0x80) | |
a582bbc3 TG |
80 | #define tmp acc |
81 | MOV (tmp, i2) | |
82 | LSR (tmp) | |
e389879f | 83 | OR (s, tmp) |
df192822 | 84 | #undef tmp |
3b86ca43 TG |
85 | |
86 | //voice 1: | |
87 | LDI (x, 1) | |
88 | MOV (t, n) | |
9401049b | 89 | LDI (o, 4) |
965274e2 | 90 | RCALL g(); |
46a8d83c | 91 | MOV (acc, t) |
3b86ca43 TG |
92 | |
93 | //voice 2: | |
94 | MOV (x, s) | |
1b023e92 | 95 | #define tmp o |
94c4920f TG |
96 | MOV (tmp, i2) |
97 | LSL (tmp) | |
98 | LSL (tmp) | |
99 | LSL (tmp) | |
100 | MOV (t, i1) | |
4b0b7dc5 TG |
101 | SWAP (t) |
102 | ANDI (t, 0xf) | |
103 | LSR (t) | |
94c4920f | 104 | OR (t, tmp) |
1b023e92 | 105 | #undef tmp |
23872091 | 106 | EOR (t, n) |
9401049b | 107 | LDI (o, 2) |
965274e2 | 108 | RCALL g(); |
46a8d83c | 109 | ADD (acc, t) |
3b86ca43 TG |
110 | |
111 | //voice 3: | |
2666c079 TG |
112 | MOV (x, s) |
113 | INC (x) | |
17c5b4e9 | 114 | #define tmp o |
a7a7abba | 115 | MOV (tmp, x) |
f84bcb7f | 116 | LSR (tmp) |
546b5bab TG |
117 | LSR (tmp) |
118 | ADD (tmp, x) | |
119 | ROR (tmp) | |
546b5bab TG |
120 | LSR (tmp) |
121 | ADD (tmp, x) | |
122 | ROR (tmp) | |
546b5bab TG |
123 | LSR (tmp) |
124 | ADD (tmp, x) | |
125 | ROR (tmp) | |
546b5bab | 126 | LSR (tmp) |
2c94c801 | 127 | MOV (x, tmp) |
17c5b4e9 | 128 | #undef tmp |
e98ab46f TG |
129 | Ml = i2<<5 | i1>>3; |
130 | Mh = i3<<5 | i2>>3; | |
dbf91c38 | 131 | RCALL mod3(); |
18570947 | 132 | ADD (t, n) |
9401049b | 133 | LDI (o, 2) |
965274e2 | 134 | RCALL g(); |
46a8d83c | 135 | ADD (acc, t) |
3b86ca43 TG |
136 | |
137 | //voice 4: | |
6bc3ca83 TG |
138 | MOV (x, s) |
139 | INC (x) | |
140 | #define tmp o | |
86f35aa4 TG |
141 | MOV (tmp, x) |
142 | LSR (tmp) | |
143 | ADD (tmp, x) | |
144 | ROR (tmp) | |
86f35aa4 | 145 | LSR (tmp) |
86f35aa4 TG |
146 | LSR (tmp) |
147 | ADD (tmp, x) | |
148 | ROR (tmp) | |
149 | ADD (tmp, x) | |
150 | ROR (tmp) | |
86f35aa4 | 151 | LSR (tmp) |
86f35aa4 | 152 | LSR (tmp) |
c2693411 | 153 | MOV (x, tmp) |
6bc3ca83 | 154 | #undef tmp |
e98ab46f TG |
155 | Ml = i2<<6 | i1>>2; |
156 | Mh = i3<<6 | i2>>2; | |
dbf91c38 | 157 | RCALL mod3(); |
e4f7baf0 TG |
158 | SUB (t, n) |
159 | NEG (t) | |
902cfdea | 160 | SUBI (t, -8) |
9401049b | 161 | LDI (o, 1) |
965274e2 | 162 | RCALL g(); |
46a8d83c | 163 | ADD (acc, t) |
bfce2f8c | 164 | |
95fa231f | 165 | putchar(acc<<4); //TODO |
89f35588 | 166 | SUBI (i0, -1) |
95fa231f TG |
167 | ADC (i1, zero, !i0) |
168 | ADC (i2, zero, !i0&&!i1) | |
169 | ADC (i3, zero, !i0&&!i1&&!i2) | |
fe9a76e4 | 170 | } |
61fab018 | 171 | } |