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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
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10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
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14u8 x;
15u8 t;
16u8 o;
49137fbf 17u8 _;
e98ab46f 18#define Mh o //mod3 vars
dbf91c38 19#define Ml t // -"-
e98ab46f 20//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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21void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
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24 ADD (Ml, Mh)
25 CLR (Mh)
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26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
0e3d0279 32 ANDI (Ml, 0x0f)
2a69999d 33 ADD (Ml, tmp)
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34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
6c72d3c1 37 ANDI (Ml, 0x03)
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38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
c3639d5b
TG
44 CPI (Ml, 3)
45 BRPL (skip)
197a5418 46 SUBI (Ml, 3)
c3639d5b 47 skip:;
4283632d 48 RET
8d8c00e4 49 #undef tmp
e98ab46f 50}
965274e2 51void g(void) {
46a8d83c 52 // g(i, x, t, o) -> t
49137fbf 53 #define tmp _
0f219114 54 ANDI (t, 0x07)
32632e61 55 MOV (tmp, i2)
63363195 56 ANDI (tmp, 3)
09cf3949 57 TST (tmp)
49137fbf 58 #undef tmp
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59 BREQ (skip)
60 SUBI (t, -8)
61 skip:
c616f0c2 62 t = data[t];
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63 /*MOV X_hi==_, data_hi
64 MOV X_lo==t, data_lo
65 ADD X_lo, t
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66 ADC X_hi, zero
67 LD t, X */
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68 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
69 t >>= o; //NOTE: o == {1, 2, 4}
c616f0c2 70 ANDI (t, 3)
4283632d 71 RET //TODO: CALL/RET is expensive; store PC in register and RJMP, then JRMP back
61fab018
TG
72};
73
74int main(void) {
a1631438
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75 u8 n;
76 u8 s;
ab6fe4c2 77 u8 acc;
89f35588 78 //TODO: clear all vars/registers
5dd8b8ff 79 for (;;) {
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80 MOV (n, i2)
81 LSL (n)
82 LSL (n)
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83 #define tmp acc
84 MOV (tmp, i1)
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85 SWAP (tmp)
86 ANDI (tmp, 0x0f)
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87 LSR (tmp)
88 LSR (tmp)
128ff01a 89 OR (n, tmp)
bc7680e3 90 #undef tmp
df192822 91 MOV (s, i3)
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92 ROR (s)
93 ROR (s)
94 ANDI (s, 0x80)
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95 #define tmp acc
96 MOV (tmp, i2)
97 LSR (tmp)
e389879f 98 OR (s, tmp)
df192822 99 #undef tmp
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100
101 //voice 1:
102 LDI (x, 1)
103 MOV (t, n)
9401049b 104 LDI (o, 4)
965274e2 105 RCALL g();
5d9a2389 106 AND (t, x)
46a8d83c 107 MOV (acc, t)
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108
109 //voice 2:
110 MOV (x, s)
1b023e92 111 #define tmp o
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112 MOV (tmp, i2)
113 LSL (tmp)
114 LSL (tmp)
115 LSL (tmp)
116 MOV (t, i1)
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117 SWAP (t)
118 ANDI (t, 0xf)
119 LSR (t)
94c4920f 120 OR (t, tmp)
1b023e92 121 #undef tmp
23872091 122 EOR (t, n)
9401049b 123 LDI (o, 2)
965274e2 124 RCALL g();
5d9a2389 125 AND (t, x)
46a8d83c 126 ADD (acc, t)
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127
128 //voice 3:
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129 MOV (x, s)
130 INC (x)
17c5b4e9 131 #define tmp o
a7a7abba 132 MOV (tmp, x)
f84bcb7f 133 LSR (tmp)
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134 LSR (tmp)
135 ADD (tmp, x)
136 ROR (tmp)
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137 LSR (tmp)
138 ADD (tmp, x)
139 ROR (tmp)
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140 LSR (tmp)
141 ADD (tmp, x)
142 ROR (tmp)
546b5bab 143 LSR (tmp)
2c94c801 144 MOV (x, tmp)
17c5b4e9 145 #undef tmp
500692e4
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146 MOV (Ml, i2)
147 SWAP (Ml)
148 ANDI (Ml, 0xf0)
149 LSL (Ml)
150 #define tmp Mh
151 MOV (tmp, i1)
152 LSR (tmp)
153 LSR (tmp)
154 LSR (tmp)
155 OR (Ml, tmp)
156 #undef tmp
d39a46f5
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157 MOV (Mh, i3)
158 SWAP (Mh)
159 ANDI (Mh, 0xf0)
160 LSL (Mh)
161 #define tmp _
162 MOV (tmp, i2)
163 LSR (tmp)
164 LSR (tmp)
165 LSR (tmp)
166 OR (Mh, tmp)
167 #undef tmp
dbf91c38 168 RCALL mod3();
18570947 169 ADD (t, n)
9401049b 170 LDI (o, 2)
965274e2 171 RCALL g();
5d9a2389 172 AND (t, x)
46a8d83c 173 ADD (acc, t)
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174
175 //voice 4:
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176 MOV (x, s)
177 INC (x)
178 #define tmp o
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179 MOV (tmp, x)
180 LSR (tmp)
181 ADD (tmp, x)
182 ROR (tmp)
86f35aa4 183 LSR (tmp)
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184 LSR (tmp)
185 ADD (tmp, x)
186 ROR (tmp)
187 ADD (tmp, x)
188 ROR (tmp)
86f35aa4 189 LSR (tmp)
86f35aa4 190 LSR (tmp)
c2693411 191 MOV (x, tmp)
6bc3ca83 192 #undef tmp
649bb224
TG
193 MOV (Ml, i2)
194 SWAP (Ml)
195 ANDI (Ml, 0xf0)
196 LSL (Ml)
197 LSL (Ml)
198 #define tmp Mh
199 MOV (tmp, i1)
200 LSR (tmp)
201 LSR (tmp)
202 OR (Ml, tmp)
203 #undef tmp
18426c43
TG
204 MOV (Mh, i3)
205 SWAP (Mh)
206 ANDI (Mh, 0xf0)
207 LSL (Mh)
208 LSL (Mh)
209 #define tmp _
210 MOV (tmp, i2)
211 LSR (tmp)
212 LSR (tmp)
213 OR (Mh, tmp)
214 #undef tmp
dbf91c38 215 RCALL mod3();
e4f7baf0
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216 SUB (t, n)
217 NEG (t)
902cfdea 218 SUBI (t, -8)
9401049b 219 LDI (o, 1)
965274e2 220 RCALL g();
5d9a2389 221 AND (t, x)
46a8d83c 222 ADD (acc, t)
bfce2f8c 223
95fa231f 224 putchar(acc<<4); //TODO
89f35588 225 SUBI (i0, -1)
95fa231f
TG
226 ADC (i1, zero, !i0)
227 ADC (i2, zero, !i0&&!i1)
228 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 229 }
61fab018 230}
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