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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
61592bdd
TG
9u8 zero; //r16
10u8 acc; //r17
11u8 i0; //r18
12u8 i1; //r19
13u8 i2; //r20
14u8 i3; //r21
15u8 n; //r22
16u8 s; //r23
17u8 _; //r24
181efc5e 18u8 loop; //r25
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TG
19u8 t;/*==Ml*/ //r26 (Xlo)
20u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23/*fakestack_l*/ //r30 (Zlo)
24/*fakestack_h*/ //r31 (Zhi)
37bf20ea 25#define Mh x //mod3 vars
dbf91c38 26#define Ml t // -"-
e98ab46f 27//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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28void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
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31 ADD (Ml, Mh)
32 CLR (Mh)
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33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
0e3d0279 39 ANDI (Ml, 0x0f)
2a69999d 40 ADD (Ml, tmp)
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41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
6c72d3c1 44 ANDI (Ml, 0x03)
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45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
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51 CPI (Ml, 3)
52 BRPL (skip)
197a5418 53 SUBI (Ml, 3)
c3639d5b 54 skip:;
4283632d 55 RET
8d8c00e4 56 #undef tmp
e98ab46f 57}
d0324785
TG
58void mul(void) { //don't need overhead of function (inline it)
59 // i1.i0 * t -> _.x.t
60 #define a1 x
61 #define a2 _
62 #define a0 t
63 // start MUL -- 92 cycles :( (unrolled and skipping second bit: 76)
64 CLR (a2)
65 CLR (a1)
66
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67 //sorted by ocurrence, then longest cycle count first
68 CPI (t, 0x69) // most common
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69 BREQ (mul_69)
70 CPI (t, 0x75)
71 BREQ (mul_75)
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72 CPI (t, 0x9d)
73 BREQ (mul_9d)
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74 CPI (t, 0x58)
75 BREQ (mul_58)
76 CPI (t, 0x8c)
77 BREQ (mul_8c)
78 CPI (t, 0x84)
79 BREQ (mul_84)
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80 CPI (t, 0xb0)
81 BREQ (mul_b0)
6a1b7870 82 mul_58: // 0101 1000 (24cy)
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83 LSR (a2)
84 ROR (a1)
85 LSR (a2)
86 ROR (a1)
87 LSR (a2)
88 ROR (a1)
89 ADD (a1, i0)
90 ADC (a2, i1, carry)
91 LSR (a2)
92 ROR (a1)
d0324785 93
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94 ADD (a1, i0)
95 ADC (a2, i1, carry)
96 LSR (a2)
97 ROR (a1)
98 LSR (a2)
99 ROR (a1)
100 ADD (a1, i0)
101 ADC (a2, i1, carry)
102 LSR (a2)
103 ROR (a1)
104 LSR (a2)
105 ROR (a1)
44e34da0 106 RJMP (endmul)
6a1b7870 107 mul_69: // 0110 1001 (26cy)
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108 ADD (a1, i0)
109 ADC (a2, i1, carry)
110 LSR (a2)
111 ROR (a1)
112 LSR (a2)
113 ROR (a1)
114 LSR (a2)
115 ROR (a1)
116 ADD (a1, i0)
117 ADC (a2, i1, carry)
118 LSR (a2)
119 ROR (a1)
d0324785 120
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121 LSR (a2)
122 ROR (a1)
123 ADD (a1, i0)
124 ADC (a2, i1, carry)
125 LSR (a2)
126 ROR (a1)
127 ADD (a1, i0)
128 ADC (a2, i1, carry)
129 LSR (a2)
130 ROR (a1)
131 LSR (a2)
132 ROR (a1)
44e34da0 133 RJMP (endmul)
6a1b7870 134 mul_75: // 0111 0101 (28cy)
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135 ADD (a1, i0)
136 ADC (a2, i1, carry)
137 LSR (a2)
138 ROR (a1)
139 LSR (a2)
140 ROR (a1)
141 ADD (a1, i0)
142 ADC (a2, i1, carry)
143 LSR (a2)
144 ROR (a1)
145 LSR (a2)
146 ROR (a1)
d0324785 147
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148 ADD (a1, i0)
149 ADC (a2, i1, carry)
150 LSR (a2)
151 ROR (a1)
152 ADD (a1, i0)
153 ADC (a2, i1, carry)
154 LSR (a2)
155 ROR (a1)
156 ADD (a1, i0)
157 ADC (a2, i1, carry)
158 LSR (a2)
159 ROR (a1)
160 LSR (a2)
161 ROR (a1)
44e34da0 162 RJMP (endmul)
6a1b7870 163 mul_84: // 1000 0100 (22cy)
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164 LSR (a2)
165 ROR (a1)
166 LSR (a2)
167 ROR (a1)
168 ADD (a1, i0)
169 ADC (a2, i1, carry)
170 LSR (a2)
171 ROR (a1)
172 LSR (a2)
173 ROR (a1)
d0324785 174
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175 LSR (a2)
176 ROR (a1)
177 LSR (a2)
178 ROR (a1)
179 LSR (a2)
180 ROR (a1)
181 ADD (a1, i0)
182 ADC (a2, i1, carry)
183 LSR (a2)
184 ROR (a1)
44e34da0 185 RJMP (endmul)
6a1b7870 186 mul_8c: // 1000 1100 (24cy)
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187 LSR (a2)
188 ROR (a1)
189 LSR (a2)
190 ROR (a1)
191 ADD (a1, i0)
192 ADC (a2, i1, carry)
193 LSR (a2)
194 ROR (a1)
195 ADD (a1, i0)
196 ADC (a2, i1, carry)
197 LSR (a2)
198 ROR (a1)
d0324785 199
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TG
200 LSR (a2)
201 ROR (a1)
202 LSR (a2)
203 ROR (a1)
204 LSR (a2)
205 ROR (a1)
206 ADD (a1, i0)
207 ADC (a2, i1, carry)
208 LSR (a2)
209 ROR (a1)
44e34da0 210 RJMP (endmul)
6a1b7870 211 mul_9d: // 1001 1101 (28cy)
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212 ADD (a1, i0)
213 ADC (a2, i1, carry)
214 LSR (a2)
215 ROR (a1)
216 LSR (a2)
217 ROR (a1)
218 ADD (a1, i0)
219 ADC (a2, i1, carry)
220 LSR (a2)
221 ROR (a1)
222 ADD (a1, i0)
223 ADC (a2, i1, carry)
224 LSR (a2)
225 ROR (a1)
d0324785 226
30966f17
TG
227 ADD (a1, i0)
228 ADC (a2, i1, carry)
229 LSR (a2)
230 ROR (a1)
231 LSR (a2)
232 ROR (a1)
233 LSR (a2)
234 ROR (a1)
235 ADD (a1, i0)
236 ADC (a2, i1, carry)
237 LSR (a2)
238 ROR (a1)
44e34da0 239 RJMP (endmul)
6a1b7870 240 mul_b0: // 1011 0000 (22cy)
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241 LSR (a2)
242 ROR (a1)
243 LSR (a2)
244 ROR (a1)
245 LSR (a2)
246 ROR (a1)
247 LSR (a2)
248 ROR (a1)
d0324785 249
30966f17
TG
250 ADD (a1, i0)
251 ADC (a2, i1, carry)
252 LSR (a2)
253 ROR (a1)
254 ADD (a1, i0)
255 ADC (a2, i1, carry)
256 LSR (a2)
257 ROR (a1)
258 LSR (a2)
259 ROR (a1)
260 ADD (a1, i0)
261 ADC (a2, i1, carry)
262 LSR (a2)
263 ROR (a1)
44e34da0 264 endmul:
d0324785
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265
266 // end MUL
267 #undef a0
268 #undef a1
269 #undef a2
270 RET
271}
965274e2 272void g(void) {
362b33c9 273 // g(i, t) -> t
eafeaf93 274 // tempvars: `x` and `_`
49137fbf 275 #define tmp _
0f219114 276 ANDI (t, 0x07)
32632e61 277 MOV (tmp, i2)
63363195 278 ANDI (tmp, 3)
09cf3949 279 TST (tmp)
49137fbf 280 #undef tmp
09cf3949
TG
281 BREQ (skip)
282 SUBI (t, -8)
283 skip:
c616f0c2 284 t = data[t];
8ee3310e 285 /*MOV X_hi==x, data_hi
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286 MOV X_lo==t, data_lo
287 ADD X_lo, t
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288 ADC X_hi, zero
289 LD t, X */
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290 RCALL mul(); //stores used value in in x
291 MOV (t, x)
d5b74a12 292 RET //TODO: replace CALL/RET with IJMP?
61fab018
TG
293};
294
295int main(void) {
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296 CLR (zero)
297 CLR (i0)
298 CLR (i1)
299 CLR (i2)
300 CLR (i3)
5dd8b8ff 301 for (;;) {
7874ed03
TG
302 MOV (n, i2)
303 LSL (n)
304 LSL (n)
8ee3310e 305 #define tmp _
bc7680e3 306 MOV (tmp, i1)
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307 SWAP (tmp)
308 ANDI (tmp, 0x0f)
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309 LSR (tmp)
310 LSR (tmp)
128ff01a 311 OR (n, tmp)
bc7680e3 312 #undef tmp
df192822 313 MOV (s, i3)
2bbe001f 314 LSR (s)
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TG
315 ROR (s)
316 ANDI (s, 0x80)
8ee3310e 317 #define tmp _
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318 MOV (tmp, i2)
319 LSR (tmp)
e389879f 320 OR (s, tmp)
df192822 321 #undef tmp
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322
323 //voice 1:
3b86ca43 324 MOV (t, n)
965274e2 325 RCALL g();
c09a6ed8 326 SWAP (t)
9e62fea4 327 ANDI (t, 1)
46a8d83c 328 MOV (acc, t)
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329
330 //voice 2:
37bf20ea 331 #define tmp _
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TG
332 MOV (tmp, i2)
333 LSL (tmp)
334 LSL (tmp)
335 LSL (tmp)
336 MOV (t, i1)
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337 SWAP (t)
338 ANDI (t, 0xf)
339 LSR (t)
94c4920f 340 OR (t, tmp)
1b023e92 341 #undef tmp
23872091 342 EOR (t, n)
965274e2 343 RCALL g();
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TG
344 LSR (t)
345 LSR (t)
346 ANDI (t, 3)
f28def6a 347 AND (t, s)
46a8d83c 348 ADD (acc, t)
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TG
349
350 //voice 3:
500692e4
TG
351 MOV (Ml, i2)
352 SWAP (Ml)
353 ANDI (Ml, 0xf0)
354 LSL (Ml)
8ee3310e 355 #define tmp _
500692e4
TG
356 MOV (tmp, i1)
357 LSR (tmp)
358 LSR (tmp)
359 LSR (tmp)
360 OR (Ml, tmp)
361 #undef tmp
d39a46f5
TG
362 MOV (Mh, i3)
363 SWAP (Mh)
364 ANDI (Mh, 0xf0)
365 LSL (Mh)
366 #define tmp _
367 MOV (tmp, i2)
368 LSR (tmp)
369 LSR (tmp)
370 LSR (tmp)
371 OR (Mh, tmp)
372 #undef tmp
dbf91c38 373 RCALL mod3();
18570947 374 ADD (t, n)
965274e2 375 RCALL g();
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376 LSR (t)
377 LSR (t)
378 ANDI (t, 3)
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379 MOV (x, s)
380 INC (x)
37bf20ea 381 #define tmp _
f28def6a
TG
382 MOV (tmp, x)
383 LSR (tmp)
384 LSR (tmp)
385 ADD (tmp, x)
386 ROR (tmp)
387 LSR (tmp)
388 ADD (tmp, x)
389 ROR (tmp)
390 LSR (tmp)
391 ADD (tmp, x)
392 ROR (tmp)
393 LSR (tmp)
51f43293 394 AND (t, tmp)
f28def6a 395 #undef tmp
46a8d83c 396 ADD (acc, t)
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TG
397
398 //voice 4:
649bb224
TG
399 MOV (Ml, i2)
400 SWAP (Ml)
401 ANDI (Ml, 0xf0)
402 LSL (Ml)
403 LSL (Ml)
8ee3310e 404 #define tmp _
649bb224
TG
405 MOV (tmp, i1)
406 LSR (tmp)
407 LSR (tmp)
408 OR (Ml, tmp)
409 #undef tmp
18426c43
TG
410 MOV (Mh, i3)
411 SWAP (Mh)
412 ANDI (Mh, 0xf0)
413 LSL (Mh)
414 LSL (Mh)
415 #define tmp _
416 MOV (tmp, i2)
417 LSR (tmp)
418 LSR (tmp)
419 OR (Mh, tmp)
420 #undef tmp
dbf91c38 421 RCALL mod3();
e4f7baf0
TG
422 SUB (t, n)
423 NEG (t)
902cfdea 424 SUBI (t, -8)
965274e2 425 RCALL g();
c6c6cbe5
TG
426 LSR (t)
427 ANDI (t, 3)
9548359d 428 INC (s)
37bf20ea 429 #define tmp _
9548359d 430 MOV (tmp, s)
d8af0686 431 LSR (tmp)
9548359d 432 ADD (tmp, s)
d8af0686
TG
433 ROR (tmp)
434 LSR (tmp)
435 LSR (tmp)
9548359d 436 ADD (tmp, s)
d8af0686 437 ROR (tmp)
9548359d 438 ADD (tmp, s)
d8af0686
TG
439 ROR (tmp)
440 LSR (tmp)
441 LSR (tmp)
51f43293 442 AND (t, tmp)
d8af0686 443 #undef tmp
46a8d83c 444 ADD (acc, t)
bfce2f8c 445
95fa231f 446 putchar(acc<<4); //TODO
89f35588 447 SUBI (i0, -1)
95fa231f
TG
448 ADC (i1, zero, !i0)
449 ADC (i2, zero, !i0&&!i1)
450 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 451 }
61fab018 452}
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