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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
06aad1ff
TG
10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
3b86ca43 14u8 t;
abda6589 15u8 x;
49137fbf 16u8 _;
37bf20ea 17#define Mh x //mod3 vars
dbf91c38 18#define Ml t // -"-
e98ab46f 19//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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TG
20void mod3(void) {
21 // mod3(Mh.Ml) -> t
22 #define tmp _
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23 ADD (Ml, Mh)
24 CLR (Mh)
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TG
25 ADC (Mh, zero, carry) //Mh only holds the carry bit
26 MOV (tmp, Ml)
27 SWAP (tmp)
28 ANDI (tmp, 0x0f)
29 SWAP (Mh)
30 OR (tmp, Mh)
0e3d0279 31 ANDI (Ml, 0x0f)
2a69999d 32 ADD (Ml, tmp)
0fc1d6d3
TG
33 MOV (tmp, Ml)
34 LSR (tmp)
35 LSR (tmp)
6c72d3c1 36 ANDI (Ml, 0x03)
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TG
37 ADD (Ml, tmp)
38 MOV (tmp, Ml)
39 LSR (tmp)
40 LSR (tmp)
41 ANDI (Ml, 0x03)
42 ADD (Ml, tmp)
c3639d5b
TG
43 CPI (Ml, 3)
44 BRPL (skip)
197a5418 45 SUBI (Ml, 3)
c3639d5b 46 skip:;
4283632d 47 RET
8d8c00e4 48 #undef tmp
e98ab46f 49}
965274e2 50void g(void) {
362b33c9 51 // g(i, t) -> t
eafeaf93 52 // tempvars: `x` and `_`
49137fbf 53 #define tmp _
0f219114 54 ANDI (t, 0x07)
32632e61 55 MOV (tmp, i2)
63363195 56 ANDI (tmp, 3)
09cf3949 57 TST (tmp)
49137fbf 58 #undef tmp
09cf3949
TG
59 BREQ (skip)
60 SUBI (t, -8)
61 skip:
c616f0c2 62 t = data[t];
8ee3310e 63 /*MOV X_hi==x, data_hi
49137fbf
TG
64 MOV X_lo==t, data_lo
65 ADD X_lo, t
49137fbf
TG
66 ADC X_hi, zero
67 LD t, X */
e5715654 68 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
abda6589 69 RET //TODO: CALL/RET is expensive; store next-instruction-position in Z register and RJMP, then JRMP back (maybe unnecessary, since timer might need stack anyways)
61fab018
TG
70};
71
72int main(void) {
a1631438
TG
73 u8 n;
74 u8 s;
ab6fe4c2 75 u8 acc;
89f35588 76 //TODO: clear all vars/registers
5dd8b8ff 77 for (;;) {
7874ed03
TG
78 MOV (n, i2)
79 LSL (n)
80 LSL (n)
8ee3310e 81 #define tmp _
bc7680e3 82 MOV (tmp, i1)
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TG
83 SWAP (tmp)
84 ANDI (tmp, 0x0f)
3eef1ade
TG
85 LSR (tmp)
86 LSR (tmp)
128ff01a 87 OR (n, tmp)
bc7680e3 88 #undef tmp
df192822 89 MOV (s, i3)
27b03017
TG
90 ROR (s)
91 ROR (s)
92 ANDI (s, 0x80)
8ee3310e 93 #define tmp _
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94 MOV (tmp, i2)
95 LSR (tmp)
e389879f 96 OR (s, tmp)
df192822 97 #undef tmp
3b86ca43
TG
98
99 //voice 1:
3b86ca43 100 MOV (t, n)
965274e2 101 RCALL g();
c09a6ed8
TG
102 SWAP (t)
103 ANDI (t, 0x0f)
f28def6a 104 ANDI (t, 1)
46a8d83c 105 MOV (acc, t)
3b86ca43
TG
106
107 //voice 2:
37bf20ea 108 #define tmp _
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TG
109 MOV (tmp, i2)
110 LSL (tmp)
111 LSL (tmp)
112 LSL (tmp)
113 MOV (t, i1)
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TG
114 SWAP (t)
115 ANDI (t, 0xf)
116 LSR (t)
94c4920f 117 OR (t, tmp)
1b023e92 118 #undef tmp
23872091 119 EOR (t, n)
965274e2 120 RCALL g();
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121 LSR (t)
122 LSR (t)
123 ANDI (t, 3)
f28def6a 124 AND (t, s)
46a8d83c 125 ADD (acc, t)
3b86ca43
TG
126
127 //voice 3:
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TG
128 MOV (Ml, i2)
129 SWAP (Ml)
130 ANDI (Ml, 0xf0)
131 LSL (Ml)
8ee3310e 132 #define tmp _
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TG
133 MOV (tmp, i1)
134 LSR (tmp)
135 LSR (tmp)
136 LSR (tmp)
137 OR (Ml, tmp)
138 #undef tmp
d39a46f5
TG
139 MOV (Mh, i3)
140 SWAP (Mh)
141 ANDI (Mh, 0xf0)
142 LSL (Mh)
143 #define tmp _
144 MOV (tmp, i2)
145 LSR (tmp)
146 LSR (tmp)
147 LSR (tmp)
148 OR (Mh, tmp)
149 #undef tmp
dbf91c38 150 RCALL mod3();
18570947 151 ADD (t, n)
965274e2 152 RCALL g();
c6c6cbe5
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153 LSR (t)
154 LSR (t)
155 ANDI (t, 3)
f28def6a
TG
156 MOV (x, s)
157 INC (x)
37bf20ea 158 #define tmp _
f28def6a
TG
159 MOV (tmp, x)
160 LSR (tmp)
161 LSR (tmp)
162 ADD (tmp, x)
163 ROR (tmp)
164 LSR (tmp)
165 ADD (tmp, x)
166 ROR (tmp)
167 LSR (tmp)
168 ADD (tmp, x)
169 ROR (tmp)
170 LSR (tmp)
171 MOV (x, tmp)
172 #undef tmp
5d9a2389 173 AND (t, x)
46a8d83c 174 ADD (acc, t)
3b86ca43
TG
175
176 //voice 4:
649bb224
TG
177 MOV (Ml, i2)
178 SWAP (Ml)
179 ANDI (Ml, 0xf0)
180 LSL (Ml)
181 LSL (Ml)
8ee3310e 182 #define tmp _
649bb224
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183 MOV (tmp, i1)
184 LSR (tmp)
185 LSR (tmp)
186 OR (Ml, tmp)
187 #undef tmp
18426c43
TG
188 MOV (Mh, i3)
189 SWAP (Mh)
190 ANDI (Mh, 0xf0)
191 LSL (Mh)
192 LSL (Mh)
193 #define tmp _
194 MOV (tmp, i2)
195 LSR (tmp)
196 LSR (tmp)
197 OR (Mh, tmp)
198 #undef tmp
dbf91c38 199 RCALL mod3();
e4f7baf0
TG
200 SUB (t, n)
201 NEG (t)
902cfdea 202 SUBI (t, -8)
965274e2 203 RCALL g();
c6c6cbe5
TG
204 LSR (t)
205 ANDI (t, 3)
d8af0686
TG
206 MOV (x, s)
207 INC (x)
37bf20ea 208 #define tmp _
d8af0686
TG
209 MOV (tmp, x)
210 LSR (tmp)
211 ADD (tmp, x)
212 ROR (tmp)
213 LSR (tmp)
214 LSR (tmp)
215 ADD (tmp, x)
216 ROR (tmp)
217 ADD (tmp, x)
218 ROR (tmp)
219 LSR (tmp)
220 LSR (tmp)
221 MOV (x, tmp)
222 #undef tmp
5d9a2389 223 AND (t, x)
46a8d83c 224 ADD (acc, t)
bfce2f8c 225
95fa231f 226 putchar(acc<<4); //TODO
89f35588 227 SUBI (i0, -1)
95fa231f
TG
228 ADC (i1, zero, !i0)
229 ADC (i2, zero, !i0&&!i1)
230 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 231 }
61fab018 232}
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