Commit | Line | Data |
---|---|---|
61fab018 | 1 | #include <stdio.h> |
da32ed67 | 2 | #include "fakeasm.h" |
61fab018 | 3 | typedef unsigned char u8; |
da32ed67 | 4 | |
24abdcbb TG |
5 | u8 data[] = { |
6 | 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58, | |
7 | 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58 | |
8 | }; | |
61592bdd TG |
9 | u8 zero; //r16 |
10 | u8 acc; //r17 | |
11 | u8 i0; //r18 | |
12 | u8 i1; //r19 | |
13 | u8 i2; //r20 | |
14 | u8 i3; //r21 | |
15 | u8 n; //r22 | |
16 | u8 s; //r23 | |
17 | u8 _; //r24 | |
181efc5e | 18 | u8 loop; //r25 |
61592bdd TG |
19 | u8 t;/*==Ml*/ //r26 (Xlo) |
20 | u8 x;/*==Mh*/ //r27 (Xhi) | |
21 | //r28 | |
22 | //r29 | |
23 | /*fakestack_l*/ //r30 (Zlo) | |
24 | /*fakestack_h*/ //r31 (Zhi) | |
37bf20ea | 25 | #define Mh x //mod3 vars |
dbf91c38 | 26 | #define Ml t // -"- |
e98ab46f | 27 | //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml |
8d8c00e4 TG |
28 | void mod3(void) { |
29 | // mod3(Mh.Ml) -> t | |
30 | #define tmp _ | |
5b1c6cc5 TG |
31 | ADD (Ml, Mh) |
32 | CLR (Mh) | |
3d517d8a TG |
33 | ADC (Mh, zero, carry) //Mh only holds the carry bit |
34 | MOV (tmp, Ml) | |
35 | SWAP (tmp) | |
36 | ANDI (tmp, 0x0f) | |
37 | SWAP (Mh) | |
38 | OR (tmp, Mh) | |
0e3d0279 | 39 | ANDI (Ml, 0x0f) |
2a69999d | 40 | ADD (Ml, tmp) |
0fc1d6d3 TG |
41 | MOV (tmp, Ml) |
42 | LSR (tmp) | |
43 | LSR (tmp) | |
6c72d3c1 | 44 | ANDI (Ml, 0x03) |
2a69999d TG |
45 | ADD (Ml, tmp) |
46 | MOV (tmp, Ml) | |
47 | LSR (tmp) | |
48 | LSR (tmp) | |
49 | ANDI (Ml, 0x03) | |
50 | ADD (Ml, tmp) | |
c3639d5b TG |
51 | CPI (Ml, 3) |
52 | BRPL (skip) | |
197a5418 | 53 | SUBI (Ml, 3) |
c3639d5b | 54 | skip:; |
4283632d | 55 | RET |
8d8c00e4 | 56 | #undef tmp |
e98ab46f | 57 | } |
965274e2 | 58 | void g(void) { |
362b33c9 | 59 | // g(i, t) -> t |
eafeaf93 | 60 | // tempvars: `x` and `_` |
49137fbf | 61 | #define tmp _ |
0f219114 | 62 | ANDI (t, 0x07) |
32632e61 | 63 | MOV (tmp, i2) |
63363195 | 64 | ANDI (tmp, 3) |
09cf3949 | 65 | TST (tmp) |
49137fbf | 66 | #undef tmp |
09cf3949 TG |
67 | BREQ (skip) |
68 | SUBI (t, -8) | |
69 | skip: | |
c616f0c2 | 70 | t = data[t]; |
8ee3310e | 71 | /*MOV X_hi==x, data_hi |
49137fbf TG |
72 | MOV X_lo==t, data_lo |
73 | ADD X_lo, t | |
49137fbf TG |
74 | ADC X_hi, zero |
75 | LD t, X */ | |
5700437a TG |
76 | #define a1 x |
77 | #define a2 _ | |
d397f897 | 78 | #define a0 t |
b9789041 | 79 | // start MUL -- 92 cycles :( (unrolled and skipping second bit: 76) |
27ca59e7 TG |
80 | CLR (a2) |
81 | CLR (a1) | |
181efc5e TG |
82 | LDI (loop, 8) |
83 | mul: | |
e2be3b5f TG |
84 | SBRS (t, 0) |
85 | RJMP (skip2) | |
86 | ADD (a1, i0) | |
87 | ADC (a2, i1, carry) | |
88 | skip2: | |
89 | LSR (a2) | |
90 | ROR (a1) | |
91 | ROR (t) | |
92 | DEC (loop) | |
93 | BRNE (mul) | |
b9789041 | 94 | // end MUL |
181efc5e | 95 | MOV (t, a1) |
5700437a | 96 | #undef a0 |
27ca59e7 TG |
97 | #undef a1 |
98 | #undef a2 | |
d397f897 | 99 | |
d5b74a12 | 100 | RET //TODO: replace CALL/RET with IJMP? |
61fab018 TG |
101 | }; |
102 | ||
103 | int main(void) { | |
23e66ca4 TG |
104 | CLR (zero) |
105 | CLR (i0) | |
106 | CLR (i1) | |
107 | CLR (i2) | |
108 | CLR (i3) | |
5dd8b8ff | 109 | for (;;) { |
7874ed03 TG |
110 | MOV (n, i2) |
111 | LSL (n) | |
112 | LSL (n) | |
8ee3310e | 113 | #define tmp _ |
bc7680e3 | 114 | MOV (tmp, i1) |
5d4207f9 TG |
115 | SWAP (tmp) |
116 | ANDI (tmp, 0x0f) | |
3eef1ade TG |
117 | LSR (tmp) |
118 | LSR (tmp) | |
128ff01a | 119 | OR (n, tmp) |
bc7680e3 | 120 | #undef tmp |
df192822 | 121 | MOV (s, i3) |
2bbe001f | 122 | LSR (s) |
27b03017 TG |
123 | ROR (s) |
124 | ANDI (s, 0x80) | |
8ee3310e | 125 | #define tmp _ |
a582bbc3 TG |
126 | MOV (tmp, i2) |
127 | LSR (tmp) | |
e389879f | 128 | OR (s, tmp) |
df192822 | 129 | #undef tmp |
3b86ca43 TG |
130 | |
131 | //voice 1: | |
3b86ca43 | 132 | MOV (t, n) |
965274e2 | 133 | RCALL g(); |
c09a6ed8 | 134 | SWAP (t) |
9e62fea4 | 135 | ANDI (t, 1) |
46a8d83c | 136 | MOV (acc, t) |
3b86ca43 TG |
137 | |
138 | //voice 2: | |
37bf20ea | 139 | #define tmp _ |
94c4920f TG |
140 | MOV (tmp, i2) |
141 | LSL (tmp) | |
142 | LSL (tmp) | |
143 | LSL (tmp) | |
144 | MOV (t, i1) | |
4b0b7dc5 TG |
145 | SWAP (t) |
146 | ANDI (t, 0xf) | |
147 | LSR (t) | |
94c4920f | 148 | OR (t, tmp) |
1b023e92 | 149 | #undef tmp |
23872091 | 150 | EOR (t, n) |
965274e2 | 151 | RCALL g(); |
7716b427 TG |
152 | LSR (t) |
153 | LSR (t) | |
154 | ANDI (t, 3) | |
f28def6a | 155 | AND (t, s) |
46a8d83c | 156 | ADD (acc, t) |
3b86ca43 TG |
157 | |
158 | //voice 3: | |
500692e4 TG |
159 | MOV (Ml, i2) |
160 | SWAP (Ml) | |
161 | ANDI (Ml, 0xf0) | |
162 | LSL (Ml) | |
8ee3310e | 163 | #define tmp _ |
500692e4 TG |
164 | MOV (tmp, i1) |
165 | LSR (tmp) | |
166 | LSR (tmp) | |
167 | LSR (tmp) | |
168 | OR (Ml, tmp) | |
169 | #undef tmp | |
d39a46f5 TG |
170 | MOV (Mh, i3) |
171 | SWAP (Mh) | |
172 | ANDI (Mh, 0xf0) | |
173 | LSL (Mh) | |
174 | #define tmp _ | |
175 | MOV (tmp, i2) | |
176 | LSR (tmp) | |
177 | LSR (tmp) | |
178 | LSR (tmp) | |
179 | OR (Mh, tmp) | |
180 | #undef tmp | |
dbf91c38 | 181 | RCALL mod3(); |
18570947 | 182 | ADD (t, n) |
965274e2 | 183 | RCALL g(); |
c6c6cbe5 TG |
184 | LSR (t) |
185 | LSR (t) | |
186 | ANDI (t, 3) | |
f28def6a TG |
187 | MOV (x, s) |
188 | INC (x) | |
37bf20ea | 189 | #define tmp _ |
f28def6a TG |
190 | MOV (tmp, x) |
191 | LSR (tmp) | |
192 | LSR (tmp) | |
193 | ADD (tmp, x) | |
194 | ROR (tmp) | |
195 | LSR (tmp) | |
196 | ADD (tmp, x) | |
197 | ROR (tmp) | |
198 | LSR (tmp) | |
199 | ADD (tmp, x) | |
200 | ROR (tmp) | |
201 | LSR (tmp) | |
51f43293 | 202 | AND (t, tmp) |
f28def6a | 203 | #undef tmp |
46a8d83c | 204 | ADD (acc, t) |
3b86ca43 TG |
205 | |
206 | //voice 4: | |
649bb224 TG |
207 | MOV (Ml, i2) |
208 | SWAP (Ml) | |
209 | ANDI (Ml, 0xf0) | |
210 | LSL (Ml) | |
211 | LSL (Ml) | |
8ee3310e | 212 | #define tmp _ |
649bb224 TG |
213 | MOV (tmp, i1) |
214 | LSR (tmp) | |
215 | LSR (tmp) | |
216 | OR (Ml, tmp) | |
217 | #undef tmp | |
18426c43 TG |
218 | MOV (Mh, i3) |
219 | SWAP (Mh) | |
220 | ANDI (Mh, 0xf0) | |
221 | LSL (Mh) | |
222 | LSL (Mh) | |
223 | #define tmp _ | |
224 | MOV (tmp, i2) | |
225 | LSR (tmp) | |
226 | LSR (tmp) | |
227 | OR (Mh, tmp) | |
228 | #undef tmp | |
dbf91c38 | 229 | RCALL mod3(); |
e4f7baf0 TG |
230 | SUB (t, n) |
231 | NEG (t) | |
902cfdea | 232 | SUBI (t, -8) |
965274e2 | 233 | RCALL g(); |
c6c6cbe5 TG |
234 | LSR (t) |
235 | ANDI (t, 3) | |
9548359d | 236 | INC (s) |
37bf20ea | 237 | #define tmp _ |
9548359d | 238 | MOV (tmp, s) |
d8af0686 | 239 | LSR (tmp) |
9548359d | 240 | ADD (tmp, s) |
d8af0686 TG |
241 | ROR (tmp) |
242 | LSR (tmp) | |
243 | LSR (tmp) | |
9548359d | 244 | ADD (tmp, s) |
d8af0686 | 245 | ROR (tmp) |
9548359d | 246 | ADD (tmp, s) |
d8af0686 TG |
247 | ROR (tmp) |
248 | LSR (tmp) | |
249 | LSR (tmp) | |
51f43293 | 250 | AND (t, tmp) |
d8af0686 | 251 | #undef tmp |
46a8d83c | 252 | ADD (acc, t) |
bfce2f8c | 253 | |
95fa231f | 254 | putchar(acc<<4); //TODO |
89f35588 | 255 | SUBI (i0, -1) |
95fa231f TG |
256 | ADC (i1, zero, !i0) |
257 | ADC (i2, zero, !i0&&!i1) | |
258 | ADC (i3, zero, !i0&&!i1&&!i2) | |
fe9a76e4 | 259 | } |
61fab018 | 260 | } |