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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
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10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
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14u8 x;
15u8 t;
16u8 o;
49137fbf 17u8 _;
e98ab46f 18#define Mh o //mod3 vars
dbf91c38 19#define Ml t // -"-
e98ab46f 20//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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21void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
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24 ADD (Ml, Mh)
25 CLR (Mh)
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26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
0e3d0279 32 ANDI (Ml, 0x0f)
2a69999d 33 ADD (Ml, tmp)
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34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
6c72d3c1 37 ANDI (Ml, 0x03)
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38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
c3639d5b
TG
44 CPI (Ml, 3)
45 BRPL (skip)
197a5418 46 SUBI (Ml, 3)
c3639d5b 47 skip:;
4283632d 48 RET
8d8c00e4 49 #undef tmp
e98ab46f 50}
965274e2 51void g(void) {
362b33c9 52 // g(i, t) -> t
eafeaf93 53 // tempvars: `x` and `_`
49137fbf 54 #define tmp _
0f219114 55 ANDI (t, 0x07)
32632e61 56 MOV (tmp, i2)
63363195 57 ANDI (tmp, 3)
09cf3949 58 TST (tmp)
49137fbf 59 #undef tmp
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60 BREQ (skip)
61 SUBI (t, -8)
62 skip:
c616f0c2 63 t = data[t];
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64 /*MOV X_hi==_, data_hi
65 MOV X_lo==t, data_lo
66 ADD X_lo, t
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67 ADC X_hi, zero
68 LD t, X */
e5715654 69 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
4283632d 70 RET //TODO: CALL/RET is expensive; store PC in register and RJMP, then JRMP back
61fab018
TG
71};
72
73int main(void) {
a1631438
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74 u8 n;
75 u8 s;
ab6fe4c2 76 u8 acc;
89f35588 77 //TODO: clear all vars/registers
5dd8b8ff 78 for (;;) {
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79 MOV (n, i2)
80 LSL (n)
81 LSL (n)
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82 #define tmp acc
83 MOV (tmp, i1)
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84 SWAP (tmp)
85 ANDI (tmp, 0x0f)
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86 LSR (tmp)
87 LSR (tmp)
128ff01a 88 OR (n, tmp)
bc7680e3 89 #undef tmp
df192822 90 MOV (s, i3)
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91 ROR (s)
92 ROR (s)
93 ANDI (s, 0x80)
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94 #define tmp acc
95 MOV (tmp, i2)
96 LSR (tmp)
e389879f 97 OR (s, tmp)
df192822 98 #undef tmp
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99
100 //voice 1:
3b86ca43 101 MOV (t, n)
965274e2 102 RCALL g();
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103 LDI (o, 4)
104 SWAP (t)
105 ANDI (t, 0x0f)
f28def6a 106 ANDI (t, 1)
46a8d83c 107 MOV (acc, t)
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108
109 //voice 2:
1b023e92 110 #define tmp o
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111 MOV (tmp, i2)
112 LSL (tmp)
113 LSL (tmp)
114 LSL (tmp)
115 MOV (t, i1)
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116 SWAP (t)
117 ANDI (t, 0xf)
118 LSR (t)
94c4920f 119 OR (t, tmp)
1b023e92 120 #undef tmp
23872091 121 EOR (t, n)
9401049b 122 LDI (o, 2)
965274e2 123 RCALL g();
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124 t >>= o; //NOTE: o == {1, 2, 4}
125 ANDI (t, 3)
f28def6a 126 AND (t, s)
46a8d83c 127 ADD (acc, t)
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128
129 //voice 3:
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130 MOV (Ml, i2)
131 SWAP (Ml)
132 ANDI (Ml, 0xf0)
133 LSL (Ml)
134 #define tmp Mh
135 MOV (tmp, i1)
136 LSR (tmp)
137 LSR (tmp)
138 LSR (tmp)
139 OR (Ml, tmp)
140 #undef tmp
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141 MOV (Mh, i3)
142 SWAP (Mh)
143 ANDI (Mh, 0xf0)
144 LSL (Mh)
145 #define tmp _
146 MOV (tmp, i2)
147 LSR (tmp)
148 LSR (tmp)
149 LSR (tmp)
150 OR (Mh, tmp)
151 #undef tmp
dbf91c38 152 RCALL mod3();
18570947 153 ADD (t, n)
9401049b 154 LDI (o, 2)
965274e2 155 RCALL g();
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156 t >>= o; //NOTE: o == {1, 2, 4}
157 ANDI (t, 3)
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158 MOV (x, s)
159 INC (x)
160 #define tmp o
161 MOV (tmp, x)
162 LSR (tmp)
163 LSR (tmp)
164 ADD (tmp, x)
165 ROR (tmp)
166 LSR (tmp)
167 ADD (tmp, x)
168 ROR (tmp)
169 LSR (tmp)
170 ADD (tmp, x)
171 ROR (tmp)
172 LSR (tmp)
173 MOV (x, tmp)
174 #undef tmp
5d9a2389 175 AND (t, x)
46a8d83c 176 ADD (acc, t)
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177
178 //voice 4:
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179 MOV (Ml, i2)
180 SWAP (Ml)
181 ANDI (Ml, 0xf0)
182 LSL (Ml)
183 LSL (Ml)
184 #define tmp Mh
185 MOV (tmp, i1)
186 LSR (tmp)
187 LSR (tmp)
188 OR (Ml, tmp)
189 #undef tmp
18426c43
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190 MOV (Mh, i3)
191 SWAP (Mh)
192 ANDI (Mh, 0xf0)
193 LSL (Mh)
194 LSL (Mh)
195 #define tmp _
196 MOV (tmp, i2)
197 LSR (tmp)
198 LSR (tmp)
199 OR (Mh, tmp)
200 #undef tmp
dbf91c38 201 RCALL mod3();
e4f7baf0
TG
202 SUB (t, n)
203 NEG (t)
902cfdea 204 SUBI (t, -8)
9401049b 205 LDI (o, 1)
965274e2 206 RCALL g();
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207 t >>= o; //NOTE: o == {1, 2, 4}
208 ANDI (t, 3)
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209 MOV (x, s)
210 INC (x)
211 #define tmp o
212 MOV (tmp, x)
213 LSR (tmp)
214 ADD (tmp, x)
215 ROR (tmp)
216 LSR (tmp)
217 LSR (tmp)
218 ADD (tmp, x)
219 ROR (tmp)
220 ADD (tmp, x)
221 ROR (tmp)
222 LSR (tmp)
223 LSR (tmp)
224 MOV (x, tmp)
225 #undef tmp
5d9a2389 226 AND (t, x)
46a8d83c 227 ADD (acc, t)
bfce2f8c 228
95fa231f 229 putchar(acc<<4); //TODO
89f35588 230 SUBI (i0, -1)
95fa231f
TG
231 ADC (i1, zero, !i0)
232 ADC (i2, zero, !i0&&!i1)
233 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 234 }
61fab018 235}
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