Commit | Line | Data |
---|---|---|
61fab018 | 1 | #include <stdio.h> |
da32ed67 | 2 | #include "fakeasm.h" |
61fab018 | 3 | typedef unsigned char u8; |
da32ed67 | 4 | |
24abdcbb TG |
5 | u8 data[] = { |
6 | 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58, | |
7 | 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58 | |
8 | }; | |
95fa231f | 9 | u8 zero; //zero register |
06aad1ff TG |
10 | u8 i0; |
11 | u8 i1; | |
12 | u8 i2; | |
13 | u8 i3; | |
3b86ca43 TG |
14 | u8 x; |
15 | u8 t; | |
16 | u8 o; | |
49137fbf | 17 | u8 _; |
e98ab46f | 18 | #define Mh o //mod3 vars |
dbf91c38 | 19 | #define Ml t // -"- |
e98ab46f | 20 | //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml |
8d8c00e4 TG |
21 | void mod3(void) { |
22 | // mod3(Mh.Ml) -> t | |
23 | #define tmp _ | |
5b1c6cc5 TG |
24 | ADD (Ml, Mh) |
25 | CLR (Mh) | |
3d517d8a TG |
26 | ADC (Mh, zero, carry) //Mh only holds the carry bit |
27 | MOV (tmp, Ml) | |
28 | SWAP (tmp) | |
29 | ANDI (tmp, 0x0f) | |
30 | SWAP (Mh) | |
31 | OR (tmp, Mh) | |
0e3d0279 | 32 | ANDI (Ml, 0x0f) |
2a69999d | 33 | ADD (Ml, tmp) |
0fc1d6d3 TG |
34 | MOV (tmp, Ml) |
35 | LSR (tmp) | |
36 | LSR (tmp) | |
6c72d3c1 | 37 | ANDI (Ml, 0x03) |
2a69999d TG |
38 | ADD (Ml, tmp) |
39 | MOV (tmp, Ml) | |
40 | LSR (tmp) | |
41 | LSR (tmp) | |
42 | ANDI (Ml, 0x03) | |
43 | ADD (Ml, tmp) | |
c3639d5b TG |
44 | CPI (Ml, 3) |
45 | BRPL (skip) | |
197a5418 | 46 | SUBI (Ml, 3) |
c3639d5b | 47 | skip:; |
4283632d | 48 | RET |
8d8c00e4 | 49 | #undef tmp |
e98ab46f | 50 | } |
965274e2 | 51 | void g(void) { |
362b33c9 | 52 | // g(i, t) -> t |
eafeaf93 | 53 | // tempvars: `x` and `_` |
49137fbf | 54 | #define tmp _ |
0f219114 | 55 | ANDI (t, 0x07) |
32632e61 | 56 | MOV (tmp, i2) |
63363195 | 57 | ANDI (tmp, 3) |
09cf3949 | 58 | TST (tmp) |
49137fbf | 59 | #undef tmp |
09cf3949 TG |
60 | BREQ (skip) |
61 | SUBI (t, -8) | |
62 | skip: | |
c616f0c2 | 63 | t = data[t]; |
49137fbf TG |
64 | /*MOV X_hi==_, data_hi |
65 | MOV X_lo==t, data_lo | |
66 | ADD X_lo, t | |
49137fbf TG |
67 | ADC X_hi, zero |
68 | LD t, X */ | |
e5715654 | 69 | t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO |
4283632d | 70 | RET //TODO: CALL/RET is expensive; store PC in register and RJMP, then JRMP back |
61fab018 TG |
71 | }; |
72 | ||
73 | int main(void) { | |
a1631438 TG |
74 | u8 n; |
75 | u8 s; | |
ab6fe4c2 | 76 | u8 acc; |
89f35588 | 77 | //TODO: clear all vars/registers |
5dd8b8ff | 78 | for (;;) { |
7874ed03 TG |
79 | MOV (n, i2) |
80 | LSL (n) | |
81 | LSL (n) | |
bc7680e3 TG |
82 | #define tmp acc |
83 | MOV (tmp, i1) | |
5d4207f9 TG |
84 | SWAP (tmp) |
85 | ANDI (tmp, 0x0f) | |
3eef1ade TG |
86 | LSR (tmp) |
87 | LSR (tmp) | |
128ff01a | 88 | OR (n, tmp) |
bc7680e3 | 89 | #undef tmp |
df192822 | 90 | MOV (s, i3) |
27b03017 TG |
91 | ROR (s) |
92 | ROR (s) | |
93 | ANDI (s, 0x80) | |
a582bbc3 TG |
94 | #define tmp acc |
95 | MOV (tmp, i2) | |
96 | LSR (tmp) | |
e389879f | 97 | OR (s, tmp) |
df192822 | 98 | #undef tmp |
3b86ca43 TG |
99 | |
100 | //voice 1: | |
3b86ca43 | 101 | MOV (t, n) |
965274e2 | 102 | RCALL g(); |
c09a6ed8 TG |
103 | SWAP (t) |
104 | ANDI (t, 0x0f) | |
f28def6a | 105 | ANDI (t, 1) |
46a8d83c | 106 | MOV (acc, t) |
3b86ca43 TG |
107 | |
108 | //voice 2: | |
1b023e92 | 109 | #define tmp o |
94c4920f TG |
110 | MOV (tmp, i2) |
111 | LSL (tmp) | |
112 | LSL (tmp) | |
113 | LSL (tmp) | |
114 | MOV (t, i1) | |
4b0b7dc5 TG |
115 | SWAP (t) |
116 | ANDI (t, 0xf) | |
117 | LSR (t) | |
94c4920f | 118 | OR (t, tmp) |
1b023e92 | 119 | #undef tmp |
23872091 | 120 | EOR (t, n) |
965274e2 | 121 | RCALL g(); |
7716b427 TG |
122 | LSR (t) |
123 | LSR (t) | |
124 | ANDI (t, 3) | |
f28def6a | 125 | AND (t, s) |
46a8d83c | 126 | ADD (acc, t) |
3b86ca43 TG |
127 | |
128 | //voice 3: | |
500692e4 TG |
129 | MOV (Ml, i2) |
130 | SWAP (Ml) | |
131 | ANDI (Ml, 0xf0) | |
132 | LSL (Ml) | |
133 | #define tmp Mh | |
134 | MOV (tmp, i1) | |
135 | LSR (tmp) | |
136 | LSR (tmp) | |
137 | LSR (tmp) | |
138 | OR (Ml, tmp) | |
139 | #undef tmp | |
d39a46f5 TG |
140 | MOV (Mh, i3) |
141 | SWAP (Mh) | |
142 | ANDI (Mh, 0xf0) | |
143 | LSL (Mh) | |
144 | #define tmp _ | |
145 | MOV (tmp, i2) | |
146 | LSR (tmp) | |
147 | LSR (tmp) | |
148 | LSR (tmp) | |
149 | OR (Mh, tmp) | |
150 | #undef tmp | |
dbf91c38 | 151 | RCALL mod3(); |
18570947 | 152 | ADD (t, n) |
965274e2 | 153 | RCALL g(); |
c6c6cbe5 TG |
154 | LSR (t) |
155 | LSR (t) | |
156 | ANDI (t, 3) | |
f28def6a TG |
157 | MOV (x, s) |
158 | INC (x) | |
159 | #define tmp o | |
160 | MOV (tmp, x) | |
161 | LSR (tmp) | |
162 | LSR (tmp) | |
163 | ADD (tmp, x) | |
164 | ROR (tmp) | |
165 | LSR (tmp) | |
166 | ADD (tmp, x) | |
167 | ROR (tmp) | |
168 | LSR (tmp) | |
169 | ADD (tmp, x) | |
170 | ROR (tmp) | |
171 | LSR (tmp) | |
172 | MOV (x, tmp) | |
173 | #undef tmp | |
5d9a2389 | 174 | AND (t, x) |
46a8d83c | 175 | ADD (acc, t) |
3b86ca43 TG |
176 | |
177 | //voice 4: | |
649bb224 TG |
178 | MOV (Ml, i2) |
179 | SWAP (Ml) | |
180 | ANDI (Ml, 0xf0) | |
181 | LSL (Ml) | |
182 | LSL (Ml) | |
183 | #define tmp Mh | |
184 | MOV (tmp, i1) | |
185 | LSR (tmp) | |
186 | LSR (tmp) | |
187 | OR (Ml, tmp) | |
188 | #undef tmp | |
18426c43 TG |
189 | MOV (Mh, i3) |
190 | SWAP (Mh) | |
191 | ANDI (Mh, 0xf0) | |
192 | LSL (Mh) | |
193 | LSL (Mh) | |
194 | #define tmp _ | |
195 | MOV (tmp, i2) | |
196 | LSR (tmp) | |
197 | LSR (tmp) | |
198 | OR (Mh, tmp) | |
199 | #undef tmp | |
dbf91c38 | 200 | RCALL mod3(); |
e4f7baf0 TG |
201 | SUB (t, n) |
202 | NEG (t) | |
902cfdea | 203 | SUBI (t, -8) |
965274e2 | 204 | RCALL g(); |
c6c6cbe5 TG |
205 | LSR (t) |
206 | ANDI (t, 3) | |
d8af0686 TG |
207 | MOV (x, s) |
208 | INC (x) | |
209 | #define tmp o | |
210 | MOV (tmp, x) | |
211 | LSR (tmp) | |
212 | ADD (tmp, x) | |
213 | ROR (tmp) | |
214 | LSR (tmp) | |
215 | LSR (tmp) | |
216 | ADD (tmp, x) | |
217 | ROR (tmp) | |
218 | ADD (tmp, x) | |
219 | ROR (tmp) | |
220 | LSR (tmp) | |
221 | LSR (tmp) | |
222 | MOV (x, tmp) | |
223 | #undef tmp | |
5d9a2389 | 224 | AND (t, x) |
46a8d83c | 225 | ADD (acc, t) |
bfce2f8c | 226 | |
95fa231f | 227 | putchar(acc<<4); //TODO |
89f35588 | 228 | SUBI (i0, -1) |
95fa231f TG |
229 | ADC (i1, zero, !i0) |
230 | ADC (i2, zero, !i0&&!i1) | |
231 | ADC (i3, zero, !i0&&!i1&&!i2) | |
fe9a76e4 | 232 | } |
61fab018 | 233 | } |