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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG		 5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
61592bdd
TG		 9u8 zero; //r16
10u8 acc; //r17
11u8 i0; //r18
12u8 i1; //r19
13u8 i2; //r20
14u8 i3; //r21
15u8 n; //r22
16u8 s; //r23
17u8 _; //r24
181efc5e 18u8 loop; //r25
61592bdd
TG		 19u8 t;/*==Ml*/ //r26 (Xlo)
20u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23/*fakestack_l*/ //r30 (Zlo)
24/*fakestack_h*/ //r31 (Zhi)
37bf20ea 25#define Mh x //mod3 vars
dbf91c38 26#define Ml t // -"-
e98ab46f 27//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
8d8c00e4
TG		 28void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
5b1c6cc5
TG		 31 ADD (Ml, Mh)
32 CLR (Mh)
3d517d8a
TG		 33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
0e3d0279 39 ANDI (Ml, 0x0f)
2a69999d 40 ADD (Ml, tmp)
0fc1d6d3
TG		 41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
6c72d3c1 44 ANDI (Ml, 0x03)
2a69999d
TG		 45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
c3639d5b
TG		 51 CPI (Ml, 3)
52 BRPL (skip)
197a5418 53 SUBI (Ml, 3)
c3639d5b 54 skip:;
4283632d 55 RET
8d8c00e4 56 #undef tmp
e98ab46f 57}
d0324785
TG		 58void mul(void) { //don't need overhead of function (inline it)
59 // i1.i0 * t -> _.x.t
60 #define a1 x
61 #define a2 _
62 #define a0 t
63 // start MUL -- 92 cycles :( (unrolled and skipping second bit: 76)
64 CLR (a2)
65 CLR (a1)
66
67 #define MUL_ADD_ROR \
68 ADD (a1, i0) \
69 ADC (a2, i1, carry) \
70 MUL_ROR
71
72 #define MUL_ROR \
73 LSR (a2) \
74 ROR (a1) \
75 ROR (t) //superfluous?
76
77 switch(t) {
78 case 0x58: // 0101 1000
79 MUL_ROR
80 MUL_ROR
81 MUL_ROR
82 MUL_ADD_ROR
83
84 MUL_ADD_ROR
85 MUL_ROR
86 MUL_ADD_ROR
87 MUL_ROR
88 break;
89 case 0x69: // 0110 1001
90 MUL_ADD_ROR
91 MUL_ROR
92 MUL_ROR
93 MUL_ADD_ROR
94
95 MUL_ROR
96 MUL_ADD_ROR
97 MUL_ADD_ROR
98 MUL_ROR
99 break;
100 case 0x75: // 0111 0101
101 MUL_ADD_ROR
102 MUL_ROR
103 MUL_ADD_ROR
104 MUL_ROR
105
106 MUL_ADD_ROR
107 MUL_ADD_ROR
108 MUL_ADD_ROR
109 MUL_ROR
110 break;
111 case 0x84: // 1000 0100
112 MUL_ROR
113 MUL_ROR
114 MUL_ADD_ROR
115 MUL_ROR
116
117 MUL_ROR
118 MUL_ROR
119 MUL_ROR
120 MUL_ADD_ROR
121 break;
122 case 0x8c: // 1000 1100
123 MUL_ROR
124 MUL_ROR
125 MUL_ADD_ROR
126 MUL_ADD_ROR
127
128 MUL_ROR
129 MUL_ROR
130 MUL_ROR
131 MUL_ADD_ROR
132 break;
133 case 0x9d: // 1001 1101
134 MUL_ADD_ROR
135 MUL_ROR
136 MUL_ADD_ROR
137 MUL_ADD_ROR
138
139 MUL_ADD_ROR
140 MUL_ROR
141 MUL_ROR
142 MUL_ADD_ROR
143 break;
144 case 0xb0: // 1011 0000
145 MUL_ROR
146 MUL_ROR
147 MUL_ROR
148 MUL_ROR
149
150 MUL_ADD_ROR
151 MUL_ADD_ROR
152 MUL_ROR
153 MUL_ADD_ROR
154 }
155
156 // end MUL
157 #undef a0
158 #undef a1
159 #undef a2
160 RET
161}
965274e2 162void g(void) {
362b33c9 163 // g(i, t) -> t
eafeaf93 164 // tempvars: `x` and `_`
49137fbf 165 #define tmp _
0f219114 166 ANDI (t, 0x07)
32632e61 167 MOV (tmp, i2)
63363195 168 ANDI (tmp, 3)
09cf3949 169 TST (tmp)
49137fbf 170 #undef tmp
09cf3949
TG		 171 BREQ (skip)
172 SUBI (t, -8)
173 skip:
c616f0c2 174 t = data[t];
8ee3310e 175 /*MOV X_hi==x, data_hi
49137fbf
TG		 176 MOV X_lo==t, data_lo
177 ADD X_lo, t
49137fbf
TG		 178 ADC X_hi, zero
179 LD t, X */
d0324785
TG		 180 RCALL mul(); //stores used value in in x
181 MOV (t, x)
d5b74a12 182 RET //TODO: replace CALL/RET with IJMP?
61fab018
TG		 183};
184
185int main(void) {
23e66ca4
TG		 186 CLR (zero)
187 CLR (i0)
188 CLR (i1)
189 CLR (i2)
190 CLR (i3)
5dd8b8ff 191 for (;;) {
7874ed03
TG		 192 MOV (n, i2)
193 LSL (n)
194 LSL (n)
8ee3310e 195 #define tmp _
bc7680e3 196 MOV (tmp, i1)
5d4207f9
TG		 197 SWAP (tmp)
198 ANDI (tmp, 0x0f)
3eef1ade
TG		 199 LSR (tmp)
200 LSR (tmp)
128ff01a 201 OR (n, tmp)
bc7680e3 202 #undef tmp
df192822 203 MOV (s, i3)
2bbe001f 204 LSR (s)
27b03017
TG		 205 ROR (s)
206 ANDI (s, 0x80)
8ee3310e 207 #define tmp _
a582bbc3
TG		 208 MOV (tmp, i2)
209 LSR (tmp)
e389879f 210 OR (s, tmp)
df192822 211 #undef tmp
3b86ca43
TG		 212
213 //voice 1:
3b86ca43 214 MOV (t, n)
965274e2 215 RCALL g();
c09a6ed8 216 SWAP (t)
9e62fea4 217 ANDI (t, 1)
46a8d83c 218 MOV (acc, t)
3b86ca43
TG		 219
220 //voice 2:
37bf20ea 221 #define tmp _
94c4920f
TG		 222 MOV (tmp, i2)
223 LSL (tmp)
224 LSL (tmp)
225 LSL (tmp)
226 MOV (t, i1)
4b0b7dc5
TG		 227 SWAP (t)
228 ANDI (t, 0xf)
229 LSR (t)
94c4920f 230 OR (t, tmp)
1b023e92 231 #undef tmp
23872091 232 EOR (t, n)
965274e2 233 RCALL g();
7716b427
TG		 234 LSR (t)
235 LSR (t)
236 ANDI (t, 3)
f28def6a 237 AND (t, s)
46a8d83c 238 ADD (acc, t)
3b86ca43
TG		 239
240 //voice 3:
500692e4
TG		 241 MOV (Ml, i2)
242 SWAP (Ml)
243 ANDI (Ml, 0xf0)
244 LSL (Ml)
8ee3310e 245 #define tmp _
500692e4
TG		 246 MOV (tmp, i1)
247 LSR (tmp)
248 LSR (tmp)
249 LSR (tmp)
250 OR (Ml, tmp)
251 #undef tmp
d39a46f5
TG		 252 MOV (Mh, i3)
253 SWAP (Mh)
254 ANDI (Mh, 0xf0)
255 LSL (Mh)
256 #define tmp _
257 MOV (tmp, i2)
258 LSR (tmp)
259 LSR (tmp)
260 LSR (tmp)
261 OR (Mh, tmp)
262 #undef tmp
dbf91c38 263 RCALL mod3();
18570947 264 ADD (t, n)
965274e2 265 RCALL g();
c6c6cbe5
TG		 266 LSR (t)
267 LSR (t)
268 ANDI (t, 3)
f28def6a
TG		 269 MOV (x, s)
270 INC (x)
37bf20ea 271 #define tmp _
f28def6a
TG		 272 MOV (tmp, x)
273 LSR (tmp)
274 LSR (tmp)
275 ADD (tmp, x)
276 ROR (tmp)
277 LSR (tmp)
278 ADD (tmp, x)
279 ROR (tmp)
280 LSR (tmp)
281 ADD (tmp, x)
282 ROR (tmp)
283 LSR (tmp)
51f43293 284 AND (t, tmp)
f28def6a 285 #undef tmp
46a8d83c 286 ADD (acc, t)
3b86ca43
TG		 287
288 //voice 4:
649bb224
TG		 289 MOV (Ml, i2)
290 SWAP (Ml)
291 ANDI (Ml, 0xf0)
292 LSL (Ml)
293 LSL (Ml)
8ee3310e 294 #define tmp _
649bb224
TG		 295 MOV (tmp, i1)
296 LSR (tmp)
297 LSR (tmp)
298 OR (Ml, tmp)
299 #undef tmp
18426c43
TG		 300 MOV (Mh, i3)
301 SWAP (Mh)
302 ANDI (Mh, 0xf0)
303 LSL (Mh)
304 LSL (Mh)
305 #define tmp _
306 MOV (tmp, i2)
307 LSR (tmp)
308 LSR (tmp)
309 OR (Mh, tmp)
310 #undef tmp
dbf91c38 311 RCALL mod3();
e4f7baf0
TG		 312 SUB (t, n)
313 NEG (t)
902cfdea 314 SUBI (t, -8)
965274e2 315 RCALL g();
c6c6cbe5
TG		 316 LSR (t)
317 ANDI (t, 3)
9548359d 318 INC (s)
37bf20ea 319 #define tmp _
9548359d 320 MOV (tmp, s)
d8af0686 321 LSR (tmp)
9548359d 322 ADD (tmp, s)
d8af0686
TG		 323 ROR (tmp)
324 LSR (tmp)
325 LSR (tmp)
9548359d 326 ADD (tmp, s)
d8af0686 327 ROR (tmp)
9548359d 328 ADD (tmp, s)
d8af0686
TG		 329 ROR (tmp)
330 LSR (tmp)
331 LSR (tmp)
51f43293 332 AND (t, tmp)
d8af0686 333 #undef tmp
46a8d83c 334 ADD (acc, t)
bfce2f8c 335
95fa231f 336 putchar(acc<<4); //TODO
89f35588 337 SUBI (i0, -1)
95fa231f
TG		 338 ADC (i1, zero, !i0)
339 ADC (i2, zero, !i0&&!i1)
340 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 341 }
61fab018 342}
Chiptunes on an ATTiny4 (35c3 lightling talk)
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