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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
61592bdd
TG
9u8 zero; //r16
10u8 acc; //r17
11u8 i0; //r18
12u8 i1; //r19
13u8 i2; //r20
14u8 i3; //r21
15u8 n; //r22
16u8 s; //r23
17u8 _; //r24
181efc5e 18u8 loop; //r25
61592bdd
TG
19u8 t;/*==Ml*/ //r26 (Xlo)
20u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23/*fakestack_l*/ //r30 (Zlo)
24/*fakestack_h*/ //r31 (Zhi)
37bf20ea 25#define Mh x //mod3 vars
dbf91c38 26#define Ml t // -"-
e98ab46f 27//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
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28void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
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31 ADD (Ml, Mh)
32 CLR (Mh)
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33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
0e3d0279 39 ANDI (Ml, 0x0f)
2a69999d 40 ADD (Ml, tmp)
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41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
6c72d3c1 44 ANDI (Ml, 0x03)
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45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
c3639d5b
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51 CPI (Ml, 3)
52 BRPL (skip)
197a5418 53 SUBI (Ml, 3)
c3639d5b 54 skip:;
4283632d 55 RET
8d8c00e4 56 #undef tmp
e98ab46f 57}
d35c3d70
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58void g(void) {
59 // g(i, t) -> t
60 // tempvars: `x` and `_`
61 #define tmp _
62 ANDI (t, 0x07)
63 MOV (tmp, i2)
64 ANDI (tmp, 3)
65 TST (tmp)
66 #undef tmp
67 BREQ (skip)
68 SUBI (t, -8)
69 skip:
70 t = data[t];
71 /*MOV X_hi==x, data_hi
72 MOV X_lo==t, data_lo
73 ADD X_lo, t
74 ADC X_hi, zero
75 LD t, X */
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76 #define a1 x
77 #define a2 _
78 #define a0 t
d35c3d70 79 // start MUL
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80 CLR (a2)
81 CLR (a1)
82
6a1b7870 83 //sorted by ocurrence, then longest cycle count first
d35c3d70 84 CPI (t, 0x69)
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85 BREQ (mul_69)
86 CPI (t, 0x75)
87 BREQ (mul_75)
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88 CPI (t, 0x9d)
89 BREQ (mul_9d)
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90 CPI (t, 0x58)
91 BREQ (mul_58)
92 CPI (t, 0x8c)
93 BREQ (mul_8c)
94 CPI (t, 0x84)
95 BREQ (mul_84)
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96 CPI (t, 0xb0)
97 BREQ (mul_b0)
6a1b7870 98 mul_58: // 0101 1000 (24cy)
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99 LSR (a2)
100 ROR (a1)
101 LSR (a2)
102 ROR (a1)
103 LSR (a2)
104 ROR (a1)
105 ADD (a1, i0)
106 ADC (a2, i1, carry)
107 LSR (a2)
108 ROR (a1)
d0324785 109
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110 ADD (a1, i0)
111 ADC (a2, i1, carry)
112 LSR (a2)
113 ROR (a1)
114 LSR (a2)
115 ROR (a1)
116 ADD (a1, i0)
117 ADC (a2, i1, carry)
118 LSR (a2)
119 ROR (a1)
120 LSR (a2)
121 ROR (a1)
44e34da0 122 RJMP (endmul)
6a1b7870 123 mul_69: // 0110 1001 (26cy)
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124 ADD (a1, i0)
125 ADC (a2, i1, carry)
126 LSR (a2)
127 ROR (a1)
128 LSR (a2)
129 ROR (a1)
130 LSR (a2)
131 ROR (a1)
132 ADD (a1, i0)
133 ADC (a2, i1, carry)
134 LSR (a2)
135 ROR (a1)
d0324785 136
30966f17
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137 LSR (a2)
138 ROR (a1)
139 ADD (a1, i0)
140 ADC (a2, i1, carry)
141 LSR (a2)
142 ROR (a1)
143 ADD (a1, i0)
144 ADC (a2, i1, carry)
145 LSR (a2)
146 ROR (a1)
147 LSR (a2)
148 ROR (a1)
44e34da0 149 RJMP (endmul)
6a1b7870 150 mul_75: // 0111 0101 (28cy)
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151 ADD (a1, i0)
152 ADC (a2, i1, carry)
153 LSR (a2)
154 ROR (a1)
155 LSR (a2)
156 ROR (a1)
157 ADD (a1, i0)
158 ADC (a2, i1, carry)
159 LSR (a2)
160 ROR (a1)
161 LSR (a2)
162 ROR (a1)
d0324785 163
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164 ADD (a1, i0)
165 ADC (a2, i1, carry)
166 LSR (a2)
167 ROR (a1)
168 ADD (a1, i0)
169 ADC (a2, i1, carry)
170 LSR (a2)
171 ROR (a1)
172 ADD (a1, i0)
173 ADC (a2, i1, carry)
174 LSR (a2)
175 ROR (a1)
176 LSR (a2)
177 ROR (a1)
44e34da0 178 RJMP (endmul)
6a1b7870 179 mul_84: // 1000 0100 (22cy)
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180 LSR (a2)
181 ROR (a1)
182 LSR (a2)
183 ROR (a1)
184 ADD (a1, i0)
185 ADC (a2, i1, carry)
186 LSR (a2)
187 ROR (a1)
188 LSR (a2)
189 ROR (a1)
d0324785 190
30966f17
TG
191 LSR (a2)
192 ROR (a1)
193 LSR (a2)
194 ROR (a1)
195 LSR (a2)
196 ROR (a1)
197 ADD (a1, i0)
198 ADC (a2, i1, carry)
199 LSR (a2)
200 ROR (a1)
44e34da0 201 RJMP (endmul)
6a1b7870 202 mul_8c: // 1000 1100 (24cy)
30966f17
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203 LSR (a2)
204 ROR (a1)
205 LSR (a2)
206 ROR (a1)
207 ADD (a1, i0)
208 ADC (a2, i1, carry)
209 LSR (a2)
210 ROR (a1)
211 ADD (a1, i0)
212 ADC (a2, i1, carry)
213 LSR (a2)
214 ROR (a1)
d0324785 215
30966f17
TG
216 LSR (a2)
217 ROR (a1)
218 LSR (a2)
219 ROR (a1)
220 LSR (a2)
221 ROR (a1)
222 ADD (a1, i0)
223 ADC (a2, i1, carry)
224 LSR (a2)
225 ROR (a1)
44e34da0 226 RJMP (endmul)
6a1b7870 227 mul_9d: // 1001 1101 (28cy)
30966f17
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228 ADD (a1, i0)
229 ADC (a2, i1, carry)
230 LSR (a2)
231 ROR (a1)
232 LSR (a2)
233 ROR (a1)
234 ADD (a1, i0)
235 ADC (a2, i1, carry)
236 LSR (a2)
237 ROR (a1)
238 ADD (a1, i0)
239 ADC (a2, i1, carry)
240 LSR (a2)
241 ROR (a1)
d0324785 242
30966f17
TG
243 ADD (a1, i0)
244 ADC (a2, i1, carry)
245 LSR (a2)
246 ROR (a1)
247 LSR (a2)
248 ROR (a1)
249 LSR (a2)
250 ROR (a1)
251 ADD (a1, i0)
252 ADC (a2, i1, carry)
253 LSR (a2)
254 ROR (a1)
44e34da0 255 RJMP (endmul)
6a1b7870 256 mul_b0: // 1011 0000 (22cy)
30966f17
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257 LSR (a2)
258 ROR (a1)
259 LSR (a2)
260 ROR (a1)
261 LSR (a2)
262 ROR (a1)
263 LSR (a2)
264 ROR (a1)
d0324785 265
30966f17
TG
266 ADD (a1, i0)
267 ADC (a2, i1, carry)
268 LSR (a2)
269 ROR (a1)
270 ADD (a1, i0)
271 ADC (a2, i1, carry)
272 LSR (a2)
273 ROR (a1)
274 LSR (a2)
275 ROR (a1)
276 ADD (a1, i0)
277 ADC (a2, i1, carry)
278 LSR (a2)
279 ROR (a1)
44e34da0 280 endmul:
d0324785
TG
281 // end MUL
282 #undef a0
283 #undef a1
284 #undef a2
d0324785 285 MOV (t, x)
d5b74a12 286 RET //TODO: replace CALL/RET with IJMP?
61fab018
TG
287};
288
289int main(void) {
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290 CLR (zero)
291 CLR (i0)
292 CLR (i1)
293 CLR (i2)
294 CLR (i3)
5dd8b8ff 295 for (;;) {
7874ed03
TG
296 MOV (n, i2)
297 LSL (n)
298 LSL (n)
8ee3310e 299 #define tmp _
bc7680e3 300 MOV (tmp, i1)
5d4207f9
TG
301 SWAP (tmp)
302 ANDI (tmp, 0x0f)
3eef1ade
TG
303 LSR (tmp)
304 LSR (tmp)
128ff01a 305 OR (n, tmp)
bc7680e3 306 #undef tmp
df192822 307 MOV (s, i3)
2bbe001f 308 LSR (s)
27b03017
TG
309 ROR (s)
310 ANDI (s, 0x80)
8ee3310e 311 #define tmp _
a582bbc3
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312 MOV (tmp, i2)
313 LSR (tmp)
e389879f 314 OR (s, tmp)
df192822 315 #undef tmp
3b86ca43
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316
317 //voice 1:
3b86ca43 318 MOV (t, n)
965274e2 319 RCALL g();
c09a6ed8 320 SWAP (t)
9e62fea4 321 ANDI (t, 1)
46a8d83c 322 MOV (acc, t)
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TG
323
324 //voice 2:
37bf20ea 325 #define tmp _
94c4920f
TG
326 MOV (tmp, i2)
327 LSL (tmp)
328 LSL (tmp)
329 LSL (tmp)
330 MOV (t, i1)
4b0b7dc5
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331 SWAP (t)
332 ANDI (t, 0xf)
333 LSR (t)
94c4920f 334 OR (t, tmp)
1b023e92 335 #undef tmp
23872091 336 EOR (t, n)
965274e2 337 RCALL g();
7716b427
TG
338 LSR (t)
339 LSR (t)
340 ANDI (t, 3)
f28def6a 341 AND (t, s)
46a8d83c 342 ADD (acc, t)
3b86ca43
TG
343
344 //voice 3:
500692e4
TG
345 MOV (Ml, i2)
346 SWAP (Ml)
347 ANDI (Ml, 0xf0)
348 LSL (Ml)
8ee3310e 349 #define tmp _
500692e4
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350 MOV (tmp, i1)
351 LSR (tmp)
352 LSR (tmp)
353 LSR (tmp)
354 OR (Ml, tmp)
355 #undef tmp
d39a46f5
TG
356 MOV (Mh, i3)
357 SWAP (Mh)
358 ANDI (Mh, 0xf0)
359 LSL (Mh)
360 #define tmp _
361 MOV (tmp, i2)
362 LSR (tmp)
363 LSR (tmp)
364 LSR (tmp)
365 OR (Mh, tmp)
366 #undef tmp
dbf91c38 367 RCALL mod3();
18570947 368 ADD (t, n)
965274e2 369 RCALL g();
c6c6cbe5
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370 LSR (t)
371 LSR (t)
372 ANDI (t, 3)
f28def6a
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373 MOV (x, s)
374 INC (x)
37bf20ea 375 #define tmp _
f28def6a
TG
376 MOV (tmp, x)
377 LSR (tmp)
378 LSR (tmp)
379 ADD (tmp, x)
380 ROR (tmp)
381 LSR (tmp)
382 ADD (tmp, x)
383 ROR (tmp)
384 LSR (tmp)
385 ADD (tmp, x)
386 ROR (tmp)
387 LSR (tmp)
51f43293 388 AND (t, tmp)
f28def6a 389 #undef tmp
46a8d83c 390 ADD (acc, t)
3b86ca43
TG
391
392 //voice 4:
649bb224
TG
393 MOV (Ml, i2)
394 SWAP (Ml)
395 ANDI (Ml, 0xf0)
396 LSL (Ml)
397 LSL (Ml)
8ee3310e 398 #define tmp _
649bb224
TG
399 MOV (tmp, i1)
400 LSR (tmp)
401 LSR (tmp)
402 OR (Ml, tmp)
403 #undef tmp
18426c43
TG
404 MOV (Mh, i3)
405 SWAP (Mh)
406 ANDI (Mh, 0xf0)
407 LSL (Mh)
408 LSL (Mh)
409 #define tmp _
410 MOV (tmp, i2)
411 LSR (tmp)
412 LSR (tmp)
413 OR (Mh, tmp)
414 #undef tmp
dbf91c38 415 RCALL mod3();
e4f7baf0
TG
416 SUB (t, n)
417 NEG (t)
902cfdea 418 SUBI (t, -8)
965274e2 419 RCALL g();
c6c6cbe5
TG
420 LSR (t)
421 ANDI (t, 3)
9548359d 422 INC (s)
37bf20ea 423 #define tmp _
9548359d 424 MOV (tmp, s)
d8af0686 425 LSR (tmp)
9548359d 426 ADD (tmp, s)
d8af0686
TG
427 ROR (tmp)
428 LSR (tmp)
429 LSR (tmp)
9548359d 430 ADD (tmp, s)
d8af0686 431 ROR (tmp)
9548359d 432 ADD (tmp, s)
d8af0686
TG
433 ROR (tmp)
434 LSR (tmp)
435 LSR (tmp)
51f43293 436 AND (t, tmp)
d8af0686 437 #undef tmp
46a8d83c 438 ADD (acc, t)
bfce2f8c 439
95fa231f 440 putchar(acc<<4); //TODO
89f35588 441 SUBI (i0, -1)
95fa231f
TG
442 ADC (i1, zero, !i0)
443 ADC (i2, zero, !i0&&!i1)
444 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 445 }
61fab018 446}
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