new version
[Chiptunes.git] / foo.c
CommitLineData
61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
06aad1ff
TG
10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
3b86ca43
TG
14u8 x;
15u8 t;
16u8 o;
49137fbf 17u8 _;
e98ab46f 18#define Mh o //mod3 vars
dbf91c38 19#define Ml t // -"-
e98ab46f 20//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
8d8c00e4
TG
21void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
5b1c6cc5
TG
24 ADD (Ml, Mh)
25 CLR (Mh)
3d517d8a
TG
26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
0e3d0279 32 ANDI (Ml, 0x0f)
2a69999d 33 ADD (Ml, tmp)
0fc1d6d3
TG
34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
6c72d3c1 37 ANDI (Ml, 0x03)
2a69999d
TG
38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
c3639d5b
TG
44 CPI (Ml, 3)
45 BRPL (skip)
197a5418 46 SUBI (Ml, 3)
c3639d5b 47 skip:;
8d8c00e4 48 #undef tmp
e98ab46f 49}
965274e2 50void g(void) {
46a8d83c 51 // g(i, x, t, o) -> t
49137fbf 52 #define tmp _
0f219114 53 ANDI (t, 0x07)
32632e61 54 MOV (tmp, i2)
63363195 55 ANDI (tmp, 3)
09cf3949 56 TST (tmp)
49137fbf 57 #undef tmp
09cf3949
TG
58 BREQ (skip)
59 SUBI (t, -8)
60 skip:
c616f0c2 61 t = data[t];
49137fbf
TG
62 /*MOV X_hi==_, data_hi
63 MOV X_lo==t, data_lo
64 ADD X_lo, t
49137fbf
TG
65 ADC X_hi, zero
66 LD t, X */
e5715654
TG
67 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
68 t >>= o; //NOTE: o == {1, 2, 4}
c616f0c2
TG
69 AND (t, x)
70 ANDI (t, 3)
46a8d83c 71 RET
61fab018
TG
72};
73
74int main(void) {
a1631438
TG
75 u8 n;
76 u8 s;
ab6fe4c2 77 u8 acc;
89f35588 78 //TODO: clear all vars/registers
5dd8b8ff 79 for (;;) {
7874ed03
TG
80 MOV (n, i2)
81 LSL (n)
82 LSL (n)
bc7680e3
TG
83 #define tmp acc
84 MOV (tmp, i1)
5d4207f9
TG
85 SWAP (tmp)
86 ANDI (tmp, 0x0f)
3eef1ade
TG
87 LSR (tmp)
88 LSR (tmp)
128ff01a 89 OR (n, tmp)
bc7680e3 90 #undef tmp
df192822 91 MOV (s, i3)
27b03017
TG
92 ROR (s)
93 ROR (s)
94 ANDI (s, 0x80)
a582bbc3
TG
95 #define tmp acc
96 MOV (tmp, i2)
97 LSR (tmp)
e389879f 98 OR (s, tmp)
df192822 99 #undef tmp
3b86ca43
TG
100
101 //voice 1:
102 LDI (x, 1)
103 MOV (t, n)
9401049b 104 LDI (o, 4)
965274e2 105 RCALL g();
46a8d83c 106 MOV (acc, t)
3b86ca43
TG
107
108 //voice 2:
109 MOV (x, s)
1b023e92 110 #define tmp o
94c4920f
TG
111 MOV (tmp, i2)
112 LSL (tmp)
113 LSL (tmp)
114 LSL (tmp)
115 MOV (t, i1)
4b0b7dc5
TG
116 SWAP (t)
117 ANDI (t, 0xf)
118 LSR (t)
94c4920f 119 OR (t, tmp)
1b023e92 120 #undef tmp
23872091 121 EOR (t, n)
9401049b 122 LDI (o, 2)
965274e2 123 RCALL g();
46a8d83c 124 ADD (acc, t)
3b86ca43
TG
125
126 //voice 3:
2666c079
TG
127 MOV (x, s)
128 INC (x)
17c5b4e9 129 #define tmp o
a7a7abba 130 MOV (tmp, x)
f84bcb7f 131 LSR (tmp)
546b5bab
TG
132 LSR (tmp)
133 ADD (tmp, x)
134 ROR (tmp)
546b5bab
TG
135 LSR (tmp)
136 ADD (tmp, x)
137 ROR (tmp)
546b5bab
TG
138 LSR (tmp)
139 ADD (tmp, x)
140 ROR (tmp)
546b5bab 141 LSR (tmp)
2c94c801 142 MOV (x, tmp)
17c5b4e9 143 #undef tmp
500692e4
TG
144 MOV (Ml, i2)
145 SWAP (Ml)
146 ANDI (Ml, 0xf0)
147 LSL (Ml)
148 #define tmp Mh
149 MOV (tmp, i1)
150 LSR (tmp)
151 LSR (tmp)
152 LSR (tmp)
153 OR (Ml, tmp)
154 #undef tmp
d39a46f5
TG
155 MOV (Mh, i3)
156 SWAP (Mh)
157 ANDI (Mh, 0xf0)
158 LSL (Mh)
159 #define tmp _
160 MOV (tmp, i2)
161 LSR (tmp)
162 LSR (tmp)
163 LSR (tmp)
164 OR (Mh, tmp)
165 #undef tmp
dbf91c38 166 RCALL mod3();
18570947 167 ADD (t, n)
9401049b 168 LDI (o, 2)
965274e2 169 RCALL g();
46a8d83c 170 ADD (acc, t)
3b86ca43
TG
171
172 //voice 4:
6bc3ca83
TG
173 MOV (x, s)
174 INC (x)
175 #define tmp o
86f35aa4
TG
176 MOV (tmp, x)
177 LSR (tmp)
178 ADD (tmp, x)
179 ROR (tmp)
86f35aa4 180 LSR (tmp)
86f35aa4
TG
181 LSR (tmp)
182 ADD (tmp, x)
183 ROR (tmp)
184 ADD (tmp, x)
185 ROR (tmp)
86f35aa4 186 LSR (tmp)
86f35aa4 187 LSR (tmp)
c2693411 188 MOV (x, tmp)
6bc3ca83 189 #undef tmp
649bb224
TG
190 MOV (Ml, i2)
191 SWAP (Ml)
192 ANDI (Ml, 0xf0)
193 LSL (Ml)
194 LSL (Ml)
195 #define tmp Mh
196 MOV (tmp, i1)
197 LSR (tmp)
198 LSR (tmp)
199 OR (Ml, tmp)
200 #undef tmp
e98ab46f 201 Mh = i3<<6 | i2>>2;
dbf91c38 202 RCALL mod3();
e4f7baf0
TG
203 SUB (t, n)
204 NEG (t)
902cfdea 205 SUBI (t, -8)
9401049b 206 LDI (o, 1)
965274e2 207 RCALL g();
46a8d83c 208 ADD (acc, t)
bfce2f8c 209
95fa231f 210 putchar(acc<<4); //TODO
89f35588 211 SUBI (i0, -1)
95fa231f
TG
212 ADC (i1, zero, !i0)
213 ADC (i2, zero, !i0&&!i1)
214 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 215 }
61fab018 216}
Imprint / Impressum