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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
49137fbf 9u8 zero;
06aad1ff
TG
10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
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14u8 x;
15u8 t;
16u8 o;
49137fbf 17u8 _;
965274e2 18void g(void) {
46a8d83c 19 // g(i, x, t, o) -> t
49137fbf 20 #define tmp _
0f219114 21 ANDI (t, 0x07)
32632e61 22 MOV (tmp, i2)
63363195 23 ANDI (tmp, 3)
09cf3949 24 TST (tmp)
49137fbf 25 #undef tmp
09cf3949
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26 BREQ (skip)
27 SUBI (t, -8)
28 skip:
c616f0c2 29 t = data[t];
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30 /*MOV X_hi==_, data_hi
31 MOV X_lo==t, data_lo
32 ADD X_lo, t
33 CLR zero
34 ADC X_hi, zero
35 LD t, X */
e5715654
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36 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
37 t >>= o; //NOTE: o == {1, 2, 4}
c616f0c2
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38 AND (t, x)
39 ANDI (t, 3)
46a8d83c 40 RET
61fab018
TG
41};
42
43int main(void) {
a1631438
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44 u8 n;
45 u8 s;
ab6fe4c2 46 u8 acc;
89f35588 47 //TODO: clear all vars/registers
5dd8b8ff 48 for (;;) {
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49 MOV (n, i2)
50 LSL (n)
51 LSL (n)
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52 #define tmp acc
53 MOV (tmp, i1)
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54 SWAP (tmp)
55 ANDI (tmp, 0x0f)
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56 LSR (tmp)
57 LSR (tmp)
128ff01a 58 OR (n, tmp)
bc7680e3 59 #undef tmp
df192822 60 MOV (s, i3)
27b03017
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61 ROR (s)
62 ROR (s)
63 ANDI (s, 0x80)
a582bbc3
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64 #define tmp acc
65 MOV (tmp, i2)
66 LSR (tmp)
e389879f 67 OR (s, tmp)
df192822 68 #undef tmp
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69
70 //voice 1:
71 LDI (x, 1)
72 MOV (t, n)
9401049b 73 LDI (o, 4)
965274e2 74 RCALL g();
46a8d83c 75 MOV (acc, t)
3b86ca43
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76
77 //voice 2:
78 MOV (x, s)
1b023e92 79 #define tmp o
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80 MOV (tmp, i2)
81 LSL (tmp)
82 LSL (tmp)
83 LSL (tmp)
84 MOV (t, i1)
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85 SWAP (t)
86 ANDI (t, 0xf)
87 LSR (t)
94c4920f 88 OR (t, tmp)
1b023e92 89 #undef tmp
23872091 90 EOR (t, n)
9401049b 91 LDI (o, 2)
965274e2 92 RCALL g();
46a8d83c 93 ADD (acc, t)
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94
95 //voice 3:
2666c079
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96 MOV (x, s)
97 INC (x)
17c5b4e9 98 #define tmp o
a7a7abba 99 MOV (tmp, x)
f84bcb7f 100 LSR (tmp)
546b5bab
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101 LSR (tmp)
102 ADD (tmp, x)
103 ROR (tmp)
546b5bab
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104 LSR (tmp)
105 ADD (tmp, x)
106 ROR (tmp)
546b5bab
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107 LSR (tmp)
108 ADD (tmp, x)
109 ROR (tmp)
546b5bab 110 LSR (tmp)
2c94c801 111 MOV (x, tmp)
17c5b4e9 112 #undef tmp
49137fbf 113 t = ((i3&0x01)<<13 | i2<<5 | i1>>3) % 3; //TODO
18570947 114 ADD (t, n)
9401049b 115 LDI (o, 2)
965274e2 116 RCALL g();
46a8d83c 117 ADD (acc, t)
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118
119 //voice 4:
6bc3ca83
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120 MOV (x, s)
121 INC (x)
122 #define tmp o
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123 MOV (tmp, x)
124 LSR (tmp)
125 ADD (tmp, x)
126 ROR (tmp)
86f35aa4 127 LSR (tmp)
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128 LSR (tmp)
129 ADD (tmp, x)
130 ROR (tmp)
131 ADD (tmp, x)
132 ROR (tmp)
86f35aa4 133 LSR (tmp)
86f35aa4 134 LSR (tmp)
c2693411 135 MOV (x, tmp)
6bc3ca83 136 #undef tmp
49137fbf 137 t = ((i3&0x01)<<14 | i2<<6 | i1>>2) % 3; //TODO
e4f7baf0
TG
138 SUB (t, n)
139 NEG (t)
902cfdea 140 SUBI (t, -8)
9401049b 141 LDI (o, 1)
965274e2 142 RCALL g();
46a8d83c 143 ADD (acc, t)
bfce2f8c 144
ab6fe4c2 145 putchar(acc<<4);
89f35588 146 #define tmp acc
3df69ede 147 CLR (tmp) //NOTE: maybe use dedicated zero register?
89f35588
TG
148 SUBI (i0, -1)
149 ADC (i1, tmp, !i0)
150 ADC (i2, tmp, !i0&&!i1)
151 ADC (i3, tmp, !i0&&!i1&&!i2)
dd7bbc4a 152 #undef tmp
fe9a76e4 153 }
61fab018 154}
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