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[Chiptunes.git] / foo.c
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61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
61592bdd
TG
5u8 zero; //r16
6u8 acc; //r17
7u8 i0; //r18
8u8 i1; //r19
9u8 i2; //r20
10u8 i3; //r21
11u8 n; //r22
12u8 s; //r23
13u8 _; //r24
0f3f4522 14 //r25
e8142e8f
TG
15u8 x;/*==Ml*/ //r26 (Xlo)
16u8 t;/*==Mh*/ //r27 (Xhi)
61592bdd
TG
17 //r28
18 //r29
e8142e8f
TG
19void *Z; //r30 (Zlo)
20/*...*/ //r31 (Zhi)
37bf20ea 21#define Mh x //mod3 vars
dbf91c38 22#define Ml t // -"-
e98ab46f 23//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
8d8c00e4
TG
24void mod3(void) {
25 // mod3(Mh.Ml) -> t
26 #define tmp _
5b1c6cc5
TG
27 ADD (Ml, Mh)
28 CLR (Mh)
3d517d8a
TG
29 ADC (Mh, zero, carry) //Mh only holds the carry bit
30 MOV (tmp, Ml)
31 SWAP (tmp)
32 ANDI (tmp, 0x0f)
33 SWAP (Mh)
34 OR (tmp, Mh)
0e3d0279 35 ANDI (Ml, 0x0f)
2a69999d 36 ADD (Ml, tmp)
0fc1d6d3
TG
37 MOV (tmp, Ml)
38 LSR (tmp)
39 LSR (tmp)
6c72d3c1 40 ANDI (Ml, 0x03)
2a69999d
TG
41 ADD (Ml, tmp)
42 MOV (tmp, Ml)
43 LSR (tmp)
44 LSR (tmp)
45 ANDI (Ml, 0x03)
46 ADD (Ml, tmp)
c3639d5b
TG
47 CPI (Ml, 3)
48 BRPL (skip)
197a5418 49 SUBI (Ml, 3)
c3639d5b 50 skip:;
4283632d 51 RET
8d8c00e4 52 #undef tmp
e98ab46f 53}
d35c3d70
TG
54void g(void) {
55 // g(i, t) -> t
56 // tempvars: `x` and `_`
e8142e8f
TG
57static void* mul_jmptable[] = { // replaces data[] section at the top
58 &&mul_84, &&mul_9d, &&mul_b0, &&mul_69, &&mul_9d, &&mul_84, &&mul_69, &&mul_58,
59 &&mul_75, &&mul_8c, &&mul_b0, &&mul_69, &&mul_8c, &&mul_75, &&mul_69, &&mul_58
60 // addresses of mul_* stored in little endian (i.e. { lo(mul_84), hi(mul_84), ... })
61};
d35c3d70
TG
62 #define tmp _
63 ANDI (t, 0x07)
64 MOV (tmp, i2)
65 ANDI (tmp, 3)
66 TST (tmp)
67 #undef tmp
68 BREQ (skip)
69 SUBI (t, -8)
e8142e8f 70 skip:;
cc428230
TG
71 #define a1 x
72 #define a2 _
73 #define a0 t
74 CLR (a2)
75 CLR (a1)
e8142e8f
TG
76 goto *mul_jmptable[t]; /*
77 LDI Xlo, lo(mul_jmptable)
78 LDI Xhi, hi(mul_jmptable)
cc428230 79 ADD Xlo, t
e8142e8f
TG
80 ADC Xhi, zero
81 ADD Xlo, t ; advance twice, since it's a 16 bit address
cc428230
TG
82 ADC Xhi, zero
83 LD Zlo, X
84 SUBI Xlo, -1
85 ADC Xhi, zero
86 LD Zhi, X
e8142e8f 87 IJMP Z */
d0324785 88
6a1b7870 89 mul_58: // 0101 1000 (24cy)
30966f17
TG
90 LSR (a2)
91 ROR (a1)
92 LSR (a2)
93 ROR (a1)
94 LSR (a2)
95 ROR (a1)
96 ADD (a1, i0)
97 ADC (a2, i1, carry)
98 LSR (a2)
99 ROR (a1)
d0324785 100
30966f17
TG
101 ADD (a1, i0)
102 ADC (a2, i1, carry)
103 LSR (a2)
104 ROR (a1)
105 LSR (a2)
106 ROR (a1)
107 ADD (a1, i0)
108 ADC (a2, i1, carry)
109 LSR (a2)
110 ROR (a1)
44e34da0 111 RJMP (endmul)
6a1b7870 112 mul_69: // 0110 1001 (26cy)
30966f17
TG
113 ADD (a1, i0)
114 ADC (a2, i1, carry)
115 LSR (a2)
116 ROR (a1)
117 LSR (a2)
118 ROR (a1)
119 LSR (a2)
120 ROR (a1)
121 ADD (a1, i0)
122 ADC (a2, i1, carry)
123 LSR (a2)
124 ROR (a1)
d0324785 125
30966f17
TG
126 LSR (a2)
127 ROR (a1)
128 ADD (a1, i0)
129 ADC (a2, i1, carry)
130 LSR (a2)
131 ROR (a1)
132 ADD (a1, i0)
133 ADC (a2, i1, carry)
134 LSR (a2)
135 ROR (a1)
44e34da0 136 RJMP (endmul)
6a1b7870 137 mul_75: // 0111 0101 (28cy)
30966f17
TG
138 ADD (a1, i0)
139 ADC (a2, i1, carry)
140 LSR (a2)
141 ROR (a1)
142 LSR (a2)
143 ROR (a1)
144 ADD (a1, i0)
145 ADC (a2, i1, carry)
146 LSR (a2)
147 ROR (a1)
148 LSR (a2)
149 ROR (a1)
d0324785 150
30966f17
TG
151 ADD (a1, i0)
152 ADC (a2, i1, carry)
153 LSR (a2)
154 ROR (a1)
155 ADD (a1, i0)
156 ADC (a2, i1, carry)
157 LSR (a2)
158 ROR (a1)
159 ADD (a1, i0)
160 ADC (a2, i1, carry)
161 LSR (a2)
162 ROR (a1)
44e34da0 163 RJMP (endmul)
6a1b7870 164 mul_84: // 1000 0100 (22cy)
30966f17
TG
165 LSR (a2)
166 ROR (a1)
167 LSR (a2)
168 ROR (a1)
169 ADD (a1, i0)
170 ADC (a2, i1, carry)
171 LSR (a2)
172 ROR (a1)
173 LSR (a2)
174 ROR (a1)
d0324785 175
30966f17
TG
176 LSR (a2)
177 ROR (a1)
178 LSR (a2)
179 ROR (a1)
180 LSR (a2)
181 ROR (a1)
182 ADD (a1, i0)
183 ADC (a2, i1, carry)
44e34da0 184 RJMP (endmul)
6a1b7870 185 mul_8c: // 1000 1100 (24cy)
30966f17
TG
186 LSR (a2)
187 ROR (a1)
188 LSR (a2)
189 ROR (a1)
190 ADD (a1, i0)
191 ADC (a2, i1, carry)
192 LSR (a2)
193 ROR (a1)
194 ADD (a1, i0)
195 ADC (a2, i1, carry)
196 LSR (a2)
197 ROR (a1)
d0324785 198
30966f17
TG
199 LSR (a2)
200 ROR (a1)
201 LSR (a2)
202 ROR (a1)
203 LSR (a2)
204 ROR (a1)
205 ADD (a1, i0)
206 ADC (a2, i1, carry)
44e34da0 207 RJMP (endmul)
6a1b7870 208 mul_9d: // 1001 1101 (28cy)
30966f17
TG
209 ADD (a1, i0)
210 ADC (a2, i1, carry)
211 LSR (a2)
212 ROR (a1)
213 LSR (a2)
214 ROR (a1)
215 ADD (a1, i0)
216 ADC (a2, i1, carry)
217 LSR (a2)
218 ROR (a1)
219 ADD (a1, i0)
220 ADC (a2, i1, carry)
221 LSR (a2)
222 ROR (a1)
d0324785 223
30966f17
TG
224 ADD (a1, i0)
225 ADC (a2, i1, carry)
226 LSR (a2)
227 ROR (a1)
228 LSR (a2)
229 ROR (a1)
230 LSR (a2)
231 ROR (a1)
232 ADD (a1, i0)
233 ADC (a2, i1, carry)
44e34da0 234 RJMP (endmul)
6a1b7870 235 mul_b0: // 1011 0000 (22cy)
30966f17
TG
236 LSR (a2)
237 ROR (a1)
238 LSR (a2)
239 ROR (a1)
240 LSR (a2)
241 ROR (a1)
242 LSR (a2)
243 ROR (a1)
d0324785 244
30966f17
TG
245 ADD (a1, i0)
246 ADC (a2, i1, carry)
247 LSR (a2)
248 ROR (a1)
249 ADD (a1, i0)
250 ADC (a2, i1, carry)
251 LSR (a2)
252 ROR (a1)
253 LSR (a2)
254 ROR (a1)
255 ADD (a1, i0)
256 ADC (a2, i1, carry)
44e34da0 257 endmul:
0f3f4522
TG
258 LSR (a2) //final shift is a common operation for all
259 ROR (a1)
d0324785 260 // end MUL
0f3f4522 261 MOV (t, a1)
d0324785
TG
262 #undef a0
263 #undef a1
264 #undef a2
d5b74a12 265 RET //TODO: replace CALL/RET with IJMP?
61fab018
TG
266};
267
268int main(void) {
23e66ca4
TG
269 CLR (zero)
270 CLR (i0)
271 CLR (i1)
272 CLR (i2)
273 CLR (i3)
5dd8b8ff 274 for (;;) {
7874ed03
TG
275 MOV (n, i2)
276 LSL (n)
277 LSL (n)
8ee3310e 278 #define tmp _
bc7680e3 279 MOV (tmp, i1)
5d4207f9
TG
280 SWAP (tmp)
281 ANDI (tmp, 0x0f)
3eef1ade
TG
282 LSR (tmp)
283 LSR (tmp)
128ff01a 284 OR (n, tmp)
bc7680e3 285 #undef tmp
df192822 286 MOV (s, i3)
2bbe001f 287 LSR (s)
27b03017
TG
288 ROR (s)
289 ANDI (s, 0x80)
8ee3310e 290 #define tmp _
a582bbc3
TG
291 MOV (tmp, i2)
292 LSR (tmp)
e389879f 293 OR (s, tmp)
df192822 294 #undef tmp
3b86ca43
TG
295
296 //voice 1:
3b86ca43 297 MOV (t, n)
965274e2 298 RCALL g();
c09a6ed8 299 SWAP (t)
9e62fea4 300 ANDI (t, 1)
46a8d83c 301 MOV (acc, t)
3b86ca43
TG
302
303 //voice 2:
37bf20ea 304 #define tmp _
94c4920f
TG
305 MOV (tmp, i2)
306 LSL (tmp)
307 LSL (tmp)
308 LSL (tmp)
309 MOV (t, i1)
4b0b7dc5
TG
310 SWAP (t)
311 ANDI (t, 0xf)
312 LSR (t)
94c4920f 313 OR (t, tmp)
1b023e92 314 #undef tmp
23872091 315 EOR (t, n)
965274e2 316 RCALL g();
7716b427
TG
317 LSR (t)
318 LSR (t)
319 ANDI (t, 3)
f28def6a 320 AND (t, s)
46a8d83c 321 ADD (acc, t)
3b86ca43
TG
322
323 //voice 3:
500692e4
TG
324 MOV (Ml, i2)
325 SWAP (Ml)
326 ANDI (Ml, 0xf0)
327 LSL (Ml)
8ee3310e 328 #define tmp _
500692e4
TG
329 MOV (tmp, i1)
330 LSR (tmp)
331 LSR (tmp)
332 LSR (tmp)
333 OR (Ml, tmp)
334 #undef tmp
d39a46f5
TG
335 MOV (Mh, i3)
336 SWAP (Mh)
337 ANDI (Mh, 0xf0)
338 LSL (Mh)
339 #define tmp _
340 MOV (tmp, i2)
341 LSR (tmp)
342 LSR (tmp)
343 LSR (tmp)
344 OR (Mh, tmp)
345 #undef tmp
dbf91c38 346 RCALL mod3();
18570947 347 ADD (t, n)
965274e2 348 RCALL g();
c6c6cbe5
TG
349 LSR (t)
350 LSR (t)
351 ANDI (t, 3)
f28def6a
TG
352 MOV (x, s)
353 INC (x)
37bf20ea 354 #define tmp _
f28def6a
TG
355 MOV (tmp, x)
356 LSR (tmp)
357 LSR (tmp)
358 ADD (tmp, x)
359 ROR (tmp)
360 LSR (tmp)
361 ADD (tmp, x)
362 ROR (tmp)
363 LSR (tmp)
364 ADD (tmp, x)
365 ROR (tmp)
366 LSR (tmp)
51f43293 367 AND (t, tmp)
f28def6a 368 #undef tmp
46a8d83c 369 ADD (acc, t)
3b86ca43
TG
370
371 //voice 4:
649bb224
TG
372 MOV (Ml, i2)
373 SWAP (Ml)
374 ANDI (Ml, 0xf0)
375 LSL (Ml)
376 LSL (Ml)
8ee3310e 377 #define tmp _
649bb224
TG
378 MOV (tmp, i1)
379 LSR (tmp)
380 LSR (tmp)
381 OR (Ml, tmp)
382 #undef tmp
18426c43
TG
383 MOV (Mh, i3)
384 SWAP (Mh)
385 ANDI (Mh, 0xf0)
386 LSL (Mh)
387 LSL (Mh)
388 #define tmp _
389 MOV (tmp, i2)
390 LSR (tmp)
391 LSR (tmp)
392 OR (Mh, tmp)
393 #undef tmp
dbf91c38 394 RCALL mod3();
e4f7baf0
TG
395 SUB (t, n)
396 NEG (t)
902cfdea 397 SUBI (t, -8)
965274e2 398 RCALL g();
c6c6cbe5
TG
399 LSR (t)
400 ANDI (t, 3)
9548359d 401 INC (s)
37bf20ea 402 #define tmp _
9548359d 403 MOV (tmp, s)
d8af0686 404 LSR (tmp)
9548359d 405 ADD (tmp, s)
d8af0686
TG
406 ROR (tmp)
407 LSR (tmp)
408 LSR (tmp)
9548359d 409 ADD (tmp, s)
d8af0686 410 ROR (tmp)
9548359d 411 ADD (tmp, s)
d8af0686
TG
412 ROR (tmp)
413 LSR (tmp)
414 LSR (tmp)
51f43293 415 AND (t, tmp)
d8af0686 416 #undef tmp
46a8d83c 417 ADD (acc, t)
bfce2f8c 418
95fa231f 419 putchar(acc<<4); //TODO
89f35588 420 SUBI (i0, -1)
95fa231f
TG
421 ADC (i1, zero, !i0)
422 ADC (i2, zero, !i0&&!i1)
423 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 424 }
61fab018 425}
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