new version
[Chiptunes.git] / foo.c
CommitLineData
61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
06aad1ff
TG
10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
3b86ca43
TG
14u8 x;
15u8 t;
16u8 o;
49137fbf 17u8 _;
e98ab46f 18#define Mh o //mod3 vars
dbf91c38 19#define Ml t // -"-
e98ab46f 20//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
8d8c00e4
TG
21void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
5b1c6cc5
TG
24 ADD (Ml, Mh)
25 CLR (Mh)
3d517d8a
TG
26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
0e3d0279 32 ANDI (Ml, 0x0f)
2a69999d 33 ADD (Ml, tmp)
0fc1d6d3
TG
34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
6c72d3c1 37 ANDI (Ml, 0x03)
2a69999d
TG
38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
c3639d5b
TG
44 CPI (Ml, 3)
45 BRPL (skip)
197a5418 46 SUBI (Ml, 3)
c3639d5b 47 skip:;
4283632d 48 RET
8d8c00e4 49 #undef tmp
e98ab46f 50}
965274e2 51void g(void) {
eafeaf93
TG
52 // g(i, t, o) -> t
53 // tempvars: `x` and `_`
49137fbf 54 #define tmp _
0f219114 55 ANDI (t, 0x07)
32632e61 56 MOV (tmp, i2)
63363195 57 ANDI (tmp, 3)
09cf3949 58 TST (tmp)
49137fbf 59 #undef tmp
09cf3949
TG
60 BREQ (skip)
61 SUBI (t, -8)
62 skip:
c616f0c2 63 t = data[t];
49137fbf
TG
64 /*MOV X_hi==_, data_hi
65 MOV X_lo==t, data_lo
66 ADD X_lo, t
49137fbf
TG
67 ADC X_hi, zero
68 LD t, X */
e5715654
TG
69 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
70 t >>= o; //NOTE: o == {1, 2, 4}
c616f0c2 71 ANDI (t, 3)
4283632d 72 RET //TODO: CALL/RET is expensive; store PC in register and RJMP, then JRMP back
61fab018
TG
73};
74
75int main(void) {
a1631438
TG
76 u8 n;
77 u8 s;
ab6fe4c2 78 u8 acc;
89f35588 79 //TODO: clear all vars/registers
5dd8b8ff 80 for (;;) {
7874ed03
TG
81 MOV (n, i2)
82 LSL (n)
83 LSL (n)
bc7680e3
TG
84 #define tmp acc
85 MOV (tmp, i1)
5d4207f9
TG
86 SWAP (tmp)
87 ANDI (tmp, 0x0f)
3eef1ade
TG
88 LSR (tmp)
89 LSR (tmp)
128ff01a 90 OR (n, tmp)
bc7680e3 91 #undef tmp
df192822 92 MOV (s, i3)
27b03017
TG
93 ROR (s)
94 ROR (s)
95 ANDI (s, 0x80)
a582bbc3
TG
96 #define tmp acc
97 MOV (tmp, i2)
98 LSR (tmp)
e389879f 99 OR (s, tmp)
df192822 100 #undef tmp
3b86ca43
TG
101
102 //voice 1:
3b86ca43 103 MOV (t, n)
9401049b 104 LDI (o, 4)
965274e2 105 RCALL g();
f28def6a 106 ANDI (t, 1)
46a8d83c 107 MOV (acc, t)
3b86ca43
TG
108
109 //voice 2:
1b023e92 110 #define tmp o
94c4920f
TG
111 MOV (tmp, i2)
112 LSL (tmp)
113 LSL (tmp)
114 LSL (tmp)
115 MOV (t, i1)
4b0b7dc5
TG
116 SWAP (t)
117 ANDI (t, 0xf)
118 LSR (t)
94c4920f 119 OR (t, tmp)
1b023e92 120 #undef tmp
23872091 121 EOR (t, n)
9401049b 122 LDI (o, 2)
965274e2 123 RCALL g();
f28def6a 124 AND (t, s)
46a8d83c 125 ADD (acc, t)
3b86ca43
TG
126
127 //voice 3:
500692e4
TG
128 MOV (Ml, i2)
129 SWAP (Ml)
130 ANDI (Ml, 0xf0)
131 LSL (Ml)
132 #define tmp Mh
133 MOV (tmp, i1)
134 LSR (tmp)
135 LSR (tmp)
136 LSR (tmp)
137 OR (Ml, tmp)
138 #undef tmp
d39a46f5
TG
139 MOV (Mh, i3)
140 SWAP (Mh)
141 ANDI (Mh, 0xf0)
142 LSL (Mh)
143 #define tmp _
144 MOV (tmp, i2)
145 LSR (tmp)
146 LSR (tmp)
147 LSR (tmp)
148 OR (Mh, tmp)
149 #undef tmp
dbf91c38 150 RCALL mod3();
18570947 151 ADD (t, n)
9401049b 152 LDI (o, 2)
965274e2 153 RCALL g();
f28def6a
TG
154 MOV (x, s)
155 INC (x)
156 #define tmp o
157 MOV (tmp, x)
158 LSR (tmp)
159 LSR (tmp)
160 ADD (tmp, x)
161 ROR (tmp)
162 LSR (tmp)
163 ADD (tmp, x)
164 ROR (tmp)
165 LSR (tmp)
166 ADD (tmp, x)
167 ROR (tmp)
168 LSR (tmp)
169 MOV (x, tmp)
170 #undef tmp
5d9a2389 171 AND (t, x)
46a8d83c 172 ADD (acc, t)
3b86ca43
TG
173
174 //voice 4:
649bb224
TG
175 MOV (Ml, i2)
176 SWAP (Ml)
177 ANDI (Ml, 0xf0)
178 LSL (Ml)
179 LSL (Ml)
180 #define tmp Mh
181 MOV (tmp, i1)
182 LSR (tmp)
183 LSR (tmp)
184 OR (Ml, tmp)
185 #undef tmp
18426c43
TG
186 MOV (Mh, i3)
187 SWAP (Mh)
188 ANDI (Mh, 0xf0)
189 LSL (Mh)
190 LSL (Mh)
191 #define tmp _
192 MOV (tmp, i2)
193 LSR (tmp)
194 LSR (tmp)
195 OR (Mh, tmp)
196 #undef tmp
dbf91c38 197 RCALL mod3();
e4f7baf0
TG
198 SUB (t, n)
199 NEG (t)
902cfdea 200 SUBI (t, -8)
9401049b 201 LDI (o, 1)
965274e2 202 RCALL g();
d8af0686
TG
203 MOV (x, s)
204 INC (x)
205 #define tmp o
206 MOV (tmp, x)
207 LSR (tmp)
208 ADD (tmp, x)
209 ROR (tmp)
210 LSR (tmp)
211 LSR (tmp)
212 ADD (tmp, x)
213 ROR (tmp)
214 ADD (tmp, x)
215 ROR (tmp)
216 LSR (tmp)
217 LSR (tmp)
218 MOV (x, tmp)
219 #undef tmp
5d9a2389 220 AND (t, x)
46a8d83c 221 ADD (acc, t)
bfce2f8c 222
95fa231f 223 putchar(acc<<4); //TODO
89f35588 224 SUBI (i0, -1)
95fa231f
TG
225 ADC (i1, zero, !i0)
226 ADC (i2, zero, !i0&&!i1)
227 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 228 }
61fab018 229}
Imprint / Impressum