new version
[Chiptunes.git] / foo.c
CommitLineData
61fab018 1#include <stdio.h>
da32ed67 2#include "fakeasm.h"
61fab018 3typedef unsigned char u8;
da32ed67 4
24abdcbb
TG
5u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8};
95fa231f 9u8 zero; //zero register
06aad1ff
TG
10u8 i0;
11u8 i1;
12u8 i2;
13u8 i3;
3b86ca43
TG
14u8 x;
15u8 t;
16u8 o;
49137fbf 17u8 _;
e98ab46f 18#define Mh o //mod3 vars
dbf91c38 19#define Ml t // -"-
e98ab46f 20//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
8d8c00e4
TG
21void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
5b1c6cc5
TG
24 ADD (Ml, Mh)
25 CLR (Mh)
3d517d8a
TG
26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
0e3d0279 32 ANDI (Ml, 0x0f)
2a69999d 33 ADD (Ml, tmp)
0fc1d6d3
TG
34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
6c72d3c1 37 ANDI (Ml, 0x03)
2a69999d
TG
38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
c3639d5b
TG
44 CPI (Ml, 3)
45 BRPL (skip)
197a5418 46 SUBI (Ml, 3)
c3639d5b 47 skip:;
4283632d 48 RET
8d8c00e4 49 #undef tmp
e98ab46f 50}
965274e2 51void g(void) {
46a8d83c 52 // g(i, x, t, o) -> t
49137fbf 53 #define tmp _
0f219114 54 ANDI (t, 0x07)
32632e61 55 MOV (tmp, i2)
63363195 56 ANDI (tmp, 3)
09cf3949 57 TST (tmp)
49137fbf 58 #undef tmp
09cf3949
TG
59 BREQ (skip)
60 SUBI (t, -8)
61 skip:
c616f0c2 62 t = data[t];
49137fbf
TG
63 /*MOV X_hi==_, data_hi
64 MOV X_lo==t, data_lo
65 ADD X_lo, t
49137fbf
TG
66 ADC X_hi, zero
67 LD t, X */
e5715654
TG
68 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
69 t >>= o; //NOTE: o == {1, 2, 4}
c616f0c2 70 ANDI (t, 3)
4283632d 71 RET //TODO: CALL/RET is expensive; store PC in register and RJMP, then JRMP back
61fab018
TG
72};
73
74int main(void) {
a1631438
TG
75 u8 n;
76 u8 s;
ab6fe4c2 77 u8 acc;
89f35588 78 //TODO: clear all vars/registers
5dd8b8ff 79 for (;;) {
7874ed03
TG
80 MOV (n, i2)
81 LSL (n)
82 LSL (n)
bc7680e3
TG
83 #define tmp acc
84 MOV (tmp, i1)
5d4207f9
TG
85 SWAP (tmp)
86 ANDI (tmp, 0x0f)
3eef1ade
TG
87 LSR (tmp)
88 LSR (tmp)
128ff01a 89 OR (n, tmp)
bc7680e3 90 #undef tmp
df192822 91 MOV (s, i3)
27b03017
TG
92 ROR (s)
93 ROR (s)
94 ANDI (s, 0x80)
a582bbc3
TG
95 #define tmp acc
96 MOV (tmp, i2)
97 LSR (tmp)
e389879f 98 OR (s, tmp)
df192822 99 #undef tmp
3b86ca43
TG
100
101 //voice 1:
3b86ca43 102 MOV (t, n)
9401049b 103 LDI (o, 4)
965274e2 104 RCALL g();
f28def6a 105 ANDI (t, 1)
46a8d83c 106 MOV (acc, t)
3b86ca43
TG
107
108 //voice 2:
1b023e92 109 #define tmp o
94c4920f
TG
110 MOV (tmp, i2)
111 LSL (tmp)
112 LSL (tmp)
113 LSL (tmp)
114 MOV (t, i1)
4b0b7dc5
TG
115 SWAP (t)
116 ANDI (t, 0xf)
117 LSR (t)
94c4920f 118 OR (t, tmp)
1b023e92 119 #undef tmp
23872091 120 EOR (t, n)
9401049b 121 LDI (o, 2)
965274e2 122 RCALL g();
f28def6a 123 AND (t, s)
46a8d83c 124 ADD (acc, t)
3b86ca43
TG
125
126 //voice 3:
500692e4
TG
127 MOV (Ml, i2)
128 SWAP (Ml)
129 ANDI (Ml, 0xf0)
130 LSL (Ml)
131 #define tmp Mh
132 MOV (tmp, i1)
133 LSR (tmp)
134 LSR (tmp)
135 LSR (tmp)
136 OR (Ml, tmp)
137 #undef tmp
d39a46f5
TG
138 MOV (Mh, i3)
139 SWAP (Mh)
140 ANDI (Mh, 0xf0)
141 LSL (Mh)
142 #define tmp _
143 MOV (tmp, i2)
144 LSR (tmp)
145 LSR (tmp)
146 LSR (tmp)
147 OR (Mh, tmp)
148 #undef tmp
dbf91c38 149 RCALL mod3();
18570947 150 ADD (t, n)
9401049b 151 LDI (o, 2)
965274e2 152 RCALL g();
f28def6a
TG
153 MOV (x, s)
154 INC (x)
155 #define tmp o
156 MOV (tmp, x)
157 LSR (tmp)
158 LSR (tmp)
159 ADD (tmp, x)
160 ROR (tmp)
161 LSR (tmp)
162 ADD (tmp, x)
163 ROR (tmp)
164 LSR (tmp)
165 ADD (tmp, x)
166 ROR (tmp)
167 LSR (tmp)
168 MOV (x, tmp)
169 #undef tmp
5d9a2389 170 AND (t, x)
46a8d83c 171 ADD (acc, t)
3b86ca43
TG
172
173 //voice 4:
6bc3ca83
TG
174 MOV (x, s)
175 INC (x)
176 #define tmp o
86f35aa4
TG
177 MOV (tmp, x)
178 LSR (tmp)
179 ADD (tmp, x)
180 ROR (tmp)
86f35aa4 181 LSR (tmp)
86f35aa4
TG
182 LSR (tmp)
183 ADD (tmp, x)
184 ROR (tmp)
185 ADD (tmp, x)
186 ROR (tmp)
86f35aa4 187 LSR (tmp)
86f35aa4 188 LSR (tmp)
c2693411 189 MOV (x, tmp)
6bc3ca83 190 #undef tmp
649bb224
TG
191 MOV (Ml, i2)
192 SWAP (Ml)
193 ANDI (Ml, 0xf0)
194 LSL (Ml)
195 LSL (Ml)
196 #define tmp Mh
197 MOV (tmp, i1)
198 LSR (tmp)
199 LSR (tmp)
200 OR (Ml, tmp)
201 #undef tmp
18426c43
TG
202 MOV (Mh, i3)
203 SWAP (Mh)
204 ANDI (Mh, 0xf0)
205 LSL (Mh)
206 LSL (Mh)
207 #define tmp _
208 MOV (tmp, i2)
209 LSR (tmp)
210 LSR (tmp)
211 OR (Mh, tmp)
212 #undef tmp
dbf91c38 213 RCALL mod3();
e4f7baf0
TG
214 SUB (t, n)
215 NEG (t)
902cfdea 216 SUBI (t, -8)
9401049b 217 LDI (o, 1)
965274e2 218 RCALL g();
5d9a2389 219 AND (t, x)
46a8d83c 220 ADD (acc, t)
bfce2f8c 221
95fa231f 222 putchar(acc<<4); //TODO
89f35588 223 SUBI (i0, -1)
95fa231f
TG
224 ADC (i1, zero, !i0)
225 ADC (i2, zero, !i0&&!i1)
226 ADC (i3, zero, !i0&&!i1&&!i2)
fe9a76e4 227 }
61fab018 228}
Imprint / Impressum