| | 1 | #include <stdio.h> |
| | 2 | #include "fakeasm.h" |
| | 3 | typedef unsigned char u8; |
| | 4 | |
| | 5 | u8 data[] = { |
| | 6 | 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58, |
| | 7 | 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58 |
| | 8 | }; |
| | 9 | u8 zero; //zero register |
| | 10 | u8 i0; |
| | 11 | u8 i1; |
| | 12 | u8 i2; |
| | 13 | u8 i3; |
| | 14 | u8 x; |
| | 15 | u8 t; |
| | 16 | u8 o; |
| | 17 | u8 _; |
| | 18 | #define Mh o //mod3 vars |
| | 19 | #define Ml t // -"- |
| | 20 | void mod3(void) { //avail: t, o _ |
| | 21 | //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml |
| | 22 | #define tmp _ |
| | 23 | ADD (Ml, Mh) |
| | 24 | CLR (Mh) |
| | 25 | ADC (Mh, zero, carry) //Mh only holds the carry bit |
| | 26 | MOV (tmp, Ml) |
| | 27 | SWAP (tmp) |
| | 28 | ANDI (tmp, 0x0f) |
| | 29 | SWAP (Mh) |
| | 30 | OR (tmp, Mh) |
| | 31 | Ml = (tmp) + (Ml & 0xF); |
| | 32 | Ml = (Ml >> 2) + (Ml & 0x3); |
| | 33 | Ml = (Ml >> 2) + (Ml & 0x3); |
| | 34 | if (Ml > 2) Ml = Ml - 3; |
| | 35 | #undef tmp |
| | 36 | } |
| | 37 | void g(void) { |
| | 38 | // g(i, x, t, o) -> t |
| | 39 | #define tmp _ |
| | 40 | ANDI (t, 0x07) |
| | 41 | MOV (tmp, i2) |
| | 42 | ANDI (tmp, 3) |
| | 43 | TST (tmp) |
| | 44 | #undef tmp |
| | 45 | BREQ (skip) |
| | 46 | SUBI (t, -8) |
| | 47 | skip: |
| | 48 | t = data[t]; |
| | 49 | /*MOV X_hi==_, data_hi |
| | 50 | MOV X_lo==t, data_lo |
| | 51 | ADD X_lo, t |
| | 52 | ADC X_hi, zero |
| | 53 | LD t, X */ |
| | 54 | t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO |
| | 55 | t >>= o; //NOTE: o == {1, 2, 4} |
| | 56 | AND (t, x) |
| | 57 | ANDI (t, 3) |
| | 58 | RET |
| | 59 | }; |
| | 60 | |
| | 61 | int main(void) { |
| | 62 | u8 n; |
| | 63 | u8 s; |
| | 64 | u8 acc; |
| | 65 | //TODO: clear all vars/registers |
| | 66 | for (;;) { |
| | 67 | MOV (n, i2) |
| | 68 | LSL (n) |
| | 69 | LSL (n) |
| | 70 | #define tmp acc |
| | 71 | MOV (tmp, i1) |
| | 72 | SWAP (tmp) |
| | 73 | ANDI (tmp, 0x0f) |
| | 74 | LSR (tmp) |
| | 75 | LSR (tmp) |
| | 76 | OR (n, tmp) |
| | 77 | #undef tmp |
| | 78 | MOV (s, i3) |
| | 79 | ROR (s) |
| | 80 | ROR (s) |
| | 81 | ANDI (s, 0x80) |
| | 82 | #define tmp acc |
| | 83 | MOV (tmp, i2) |
| | 84 | LSR (tmp) |
| | 85 | OR (s, tmp) |
| | 86 | #undef tmp |
| | 87 | |
| | 88 | //voice 1: |
| | 89 | LDI (x, 1) |
| | 90 | MOV (t, n) |
| | 91 | LDI (o, 4) |
| | 92 | RCALL g(); |
| | 93 | MOV (acc, t) |
| | 94 | |
| | 95 | //voice 2: |
| | 96 | MOV (x, s) |
| | 97 | #define tmp o |
| | 98 | MOV (tmp, i2) |
| | 99 | LSL (tmp) |
| | 100 | LSL (tmp) |
| | 101 | LSL (tmp) |
| | 102 | MOV (t, i1) |
| | 103 | SWAP (t) |
| | 104 | ANDI (t, 0xf) |
| | 105 | LSR (t) |
| | 106 | OR (t, tmp) |
| | 107 | #undef tmp |
| | 108 | EOR (t, n) |
| | 109 | LDI (o, 2) |
| | 110 | RCALL g(); |
| | 111 | ADD (acc, t) |
| | 112 | |
| | 113 | //voice 3: |
| | 114 | MOV (x, s) |
| | 115 | INC (x) |
| | 116 | #define tmp o |
| | 117 | MOV (tmp, x) |
| | 118 | LSR (tmp) |
| | 119 | LSR (tmp) |
| | 120 | ADD (tmp, x) |
| | 121 | ROR (tmp) |
| | 122 | LSR (tmp) |
| | 123 | ADD (tmp, x) |
| | 124 | ROR (tmp) |
| | 125 | LSR (tmp) |
| | 126 | ADD (tmp, x) |
| | 127 | ROR (tmp) |
| | 128 | LSR (tmp) |
| | 129 | MOV (x, tmp) |
| | 130 | #undef tmp |
| | 131 | Ml = i2<<5 | i1>>3; |
| | 132 | Mh = i3<<5 | i2>>3; |
| | 133 | RCALL mod3(); |
| | 134 | ADD (t, n) |
| | 135 | LDI (o, 2) |
| | 136 | RCALL g(); |
| | 137 | ADD (acc, t) |
| | 138 | |
| | 139 | //voice 4: |
| | 140 | MOV (x, s) |
| | 141 | INC (x) |
| | 142 | #define tmp o |
| | 143 | MOV (tmp, x) |
| | 144 | LSR (tmp) |
| | 145 | ADD (tmp, x) |
| | 146 | ROR (tmp) |
| | 147 | LSR (tmp) |
| | 148 | LSR (tmp) |
| | 149 | ADD (tmp, x) |
| | 150 | ROR (tmp) |
| | 151 | ADD (tmp, x) |
| | 152 | ROR (tmp) |
| | 153 | LSR (tmp) |
| | 154 | LSR (tmp) |
| | 155 | MOV (x, tmp) |
| | 156 | #undef tmp |
| | 157 | Ml = i2<<6 | i1>>2; |
| | 158 | Mh = i3<<6 | i2>>2; |
| | 159 | RCALL mod3(); |
| | 160 | SUB (t, n) |
| | 161 | NEG (t) |
| | 162 | SUBI (t, -8) |
| | 163 | LDI (o, 1) |
| | 164 | RCALL g(); |
| | 165 | ADD (acc, t) |
| | 166 | |
| | 167 | putchar(acc<<4); //TODO |
| | 168 | SUBI (i0, -1) |
| | 169 | ADC (i1, zero, !i0) |
| | 170 | ADC (i2, zero, !i0&&!i1) |
| | 171 | ADC (i3, zero, !i0&&!i1&&!i2) |
| | 172 | } |
| | 173 | } |
git://git.gir.st / Chiptunes.git / blame_incremental