foo.c

   1 #include <stdio.h>
   2 #include "fakeasm.h"
   3 typedef unsigned char u8;
   4
   5 u8 data[] = {
   6         0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
   7         0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
   8 };
   9 u8 zero; //zero register
  10 u8 i0;
  11 u8 i1;
  12 u8 i2;
  13 u8 i3;
  14 u8 x;
  15 u8 t;
  16 u8 o;
  17 u8 _;
  18 #define Mh o //mod3 vars
  19 #define Ml t // -"-
  20 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
  21 void mod3(void) {
  22         // mod3(Mh.Ml) -> t
  23         #define tmp _
  24         ADD     (Ml, Mh)
  25         CLR     (Mh)
  26         ADC     (Mh, zero, carry) //Mh only holds the carry bit
  27         MOV     (tmp, Ml)
  28         SWAP    (tmp)
  29         ANDI    (tmp, 0x0f)
  30         SWAP    (Mh)
  31         OR      (tmp, Mh)
  32         ANDI    (Ml, 0x0f)
  33         ADD     (Ml, tmp)
  34         MOV     (tmp, Ml)
  35         LSR     (tmp)
  36         LSR     (tmp)
  37         ANDI    (Ml, 0x03)
  38         ADD     (Ml, tmp)
  39         MOV     (tmp, Ml)
  40         LSR     (tmp)
  41         LSR     (tmp)
  42         ANDI    (Ml, 0x03)
  43         ADD     (Ml, tmp)
  44         CPI     (Ml, 3)
  45         BRPL    (skip)
  46         SUBI    (Ml, 3)
  47         skip:;
  48         #undef tmp
  49 }
  50 void g(void) {
  51         // g(i, x, t, o) -> t
  52         #define tmp _
  53         ANDI    (t, 0x07)
  54         MOV     (tmp, i2)
  55         ANDI    (tmp, 3)
  56         TST     (tmp)
  57         #undef tmp
  58         BREQ    (skip)
  59         SUBI    (t, -8)
  60         skip:
  61         t = data[t];
  62         /*MOV X_hi==_, data_hi
  63           MOV X_lo==t, data_lo
  64           ADD X_lo, t
  65           ADC X_hi, zero
  66           LD  t, X         */
  67         t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
  68         t >>= o; //NOTE: o == {1, 2, 4}
  69         AND     (t, x)
  70         ANDI    (t, 3)
  71         RET
  72 };
  73
  74 int main(void) {
  75         u8 n;
  76         u8 s;
  77         u8 acc;
  78         //TODO: clear all vars/registers
  79         for (;;) {
  80                 MOV     (n, i2)
  81                 LSL     (n)
  82                 LSL     (n)
  83                 #define tmp acc
  84                 MOV     (tmp, i1)
  85                 SWAP    (tmp)
  86                 ANDI    (tmp, 0x0f)
  87                 LSR     (tmp)
  88                 LSR     (tmp)
  89                 OR      (n, tmp)
  90                 #undef tmp
  91                 MOV     (s, i3)
  92                 ROR     (s)
  93                 ROR     (s)
  94                 ANDI    (s, 0x80)
  95                 #define tmp acc
  96                 MOV     (tmp, i2)
  97                 LSR     (tmp)
  98                 OR      (s, tmp)
  99                 #undef tmp
 100
 101                 //voice 1:
 102                 LDI     (x, 1)
 103                 MOV     (t, n)
 104                 LDI     (o, 4)
 105                 RCALL   g();
 106                 MOV     (acc, t)
 107
 108                 //voice 2:
 109                 MOV     (x, s)
 110                 #define tmp o
 111                 MOV     (tmp, i2)
 112                 LSL     (tmp)
 113                 LSL     (tmp)
 114                 LSL     (tmp)
 115                 MOV     (t, i1)
 116                 SWAP    (t)
 117                 ANDI    (t, 0xf)
 118                 LSR     (t)
 119                 OR      (t, tmp)
 120                 #undef tmp
 121                 EOR     (t, n)
 122                 LDI     (o, 2)
 123                 RCALL   g();
 124                 ADD     (acc, t)
 125
 126                 //voice 3:
 127                 MOV     (x, s)
 128                 INC     (x)
 129                 #define tmp o
 130                 MOV     (tmp, x)
 131                 LSR     (tmp)
 132                 LSR     (tmp)
 133                 ADD     (tmp, x)
 134                 ROR     (tmp)
 135                 LSR     (tmp)
 136                 ADD     (tmp, x)
 137                 ROR     (tmp)
 138                 LSR     (tmp)
 139                 ADD     (tmp, x)
 140                 ROR     (tmp)
 141                 LSR     (tmp)
 142                 MOV     (x, tmp)
 143                 #undef tmp
 144                 Ml = i2<<5 | i1>>3;
 145                 Mh = i3<<5 | i2>>3;
 146                 RCALL   mod3();
 147                 ADD     (t, n)
 148                 LDI     (o, 2)
 149                 RCALL   g();
 150                 ADD     (acc, t)
 151
 152                 //voice 4:
 153                 MOV     (x, s)
 154                 INC     (x)
 155                 #define tmp o
 156                 MOV     (tmp, x)
 157                 LSR     (tmp)
 158                 ADD     (tmp, x)
 159                 ROR     (tmp)
 160                 LSR     (tmp)
 161                 LSR     (tmp)
 162                 ADD     (tmp, x)
 163                 ROR     (tmp)
 164                 ADD     (tmp, x)
 165                 ROR     (tmp)
 166                 LSR     (tmp)
 167                 LSR     (tmp)
 168                 MOV     (x, tmp)
 169                 #undef tmp
 170                 Ml = i2<<6 | i1>>2;
 171                 Mh = i3<<6 | i2>>2;
 172                 RCALL   mod3();
 173                 SUB     (t, n)
 174                 NEG     (t)
 175                 SUBI    (t, -8)
 176                 LDI     (o, 1)
 177                 RCALL   g();
 178                 ADD     (acc, t)
 179
 180                 putchar(acc<<4); //TODO
 181                 SUBI    (i0, -1)
 182                 ADC     (i1, zero, !i0)
 183                 ADC     (i2, zero, !i0&&!i1)
 184                 ADC     (i3, zero, !i0&&!i1&&!i2)
 185         }
 186 }