foo.c

   1 #include <stdio.h>
   2 #include "fakeasm.h"
   3 typedef unsigned char u8;
   4
   5 u8 data[] = {
   6         0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
   7         0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
   8 };
   9 u8 zero;        //r16
  10 u8 acc;         //r17
  11 u8 i0;          //r18
  12 u8 i1;          //r19
  13 u8 i2;          //r20
  14 u8 i3;          //r21
  15 u8 n;           //r22
  16 u8 s;           //r23
  17 u8 _;           //r24
  18                 //r25
  19 u8 t;/*==Ml*/   //r26 (Xlo)
  20 u8 x;/*==Mh*/   //r27 (Xhi)
  21                 //r28
  22                 //r29
  23 /*fakestack_l*/ //r30 (Zlo)
  24 /*fakestack_h*/ //r31 (Zhi)
  25 #define Mh x //mod3 vars
  26 #define Ml t // -"-
  27 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
  28 void mod3(void) {
  29         // mod3(Mh.Ml) -> t
  30         #define tmp _
  31         ADD     (Ml, Mh)
  32         CLR     (Mh)
  33         ADC     (Mh, zero, carry) //Mh only holds the carry bit
  34         MOV     (tmp, Ml)
  35         SWAP    (tmp)
  36         ANDI    (tmp, 0x0f)
  37         SWAP    (Mh)
  38         OR      (tmp, Mh)
  39         ANDI    (Ml, 0x0f)
  40         ADD     (Ml, tmp)
  41         MOV     (tmp, Ml)
  42         LSR     (tmp)
  43         LSR     (tmp)
  44         ANDI    (Ml, 0x03)
  45         ADD     (Ml, tmp)
  46         MOV     (tmp, Ml)
  47         LSR     (tmp)
  48         LSR     (tmp)
  49         ANDI    (Ml, 0x03)
  50         ADD     (Ml, tmp)
  51         CPI     (Ml, 3)
  52         BRPL    (skip)
  53         SUBI    (Ml, 3)
  54         skip:;
  55         RET
  56         #undef tmp
  57 }
  58 void g(void) {
  59         // g(i, t) -> t
  60         // tempvars: `x` and `_`
  61         #define tmp _
  62         ANDI    (t, 0x07)
  63         MOV     (tmp, i2)
  64         ANDI    (tmp, 3)
  65         TST     (tmp)
  66         #undef tmp
  67         BREQ    (skip)
  68         SUBI    (t, -8)
  69         skip:
  70         t = data[t];
  71         /*MOV X_hi==x, data_hi
  72           MOV X_lo==t, data_lo
  73           ADD X_lo, t
  74           ADC X_hi, zero
  75           LD  t, X         */
  76         t &= 0xfd; //hint
  77         //t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
  78
  79         u8 a2 = 0;
  80         u8 a1 = 0;
  81         #define a0 t
  82
  83         for (u8 loop = 0; loop < 8; loop++) { //Note: t&2 always zero
  84                 if (t & 1) {
  85                         a2 += i1 + ((a1+i0)>>8); //2. ADC a2, i1
  86                         a1 += i0;                //1. ADD a1, i0
  87                 }
  88                 t >>= 1; t|=a1<<7;             //3. ROR t
  89                 a1>>= 1;a1|=a2<<7;             //2. ROR a1
  90                 a2>>= 1;                       //1. LSR a2
  91         }
  92         t = a1;
  93
  94         t &= 0x1e; //hint
  95         RET //TODO: replace CALL/RET with IJMP?
  96 };
  97
  98 int main(void) {
  99         CLR     (zero)
 100         CLR     (i0)
 101         CLR     (i1)
 102         CLR     (i2)
 103         CLR     (i3)
 104         for (;;) {
 105                 MOV     (n, i2)
 106                 LSL     (n)
 107                 LSL     (n)
 108                 #define tmp _
 109                 MOV     (tmp, i1)
 110                 SWAP    (tmp)
 111                 ANDI    (tmp, 0x0f)
 112                 LSR     (tmp)
 113                 LSR     (tmp)
 114                 OR      (n, tmp)
 115                 #undef tmp
 116                 MOV     (s, i3)
 117                 LSR     (s)
 118                 ROR     (s)
 119                 ANDI    (s, 0x80)
 120                 #define tmp _
 121                 MOV     (tmp, i2)
 122                 LSR     (tmp)
 123                 OR      (s, tmp)
 124                 #undef tmp
 125
 126                 //voice 1:
 127                 MOV     (t, n)
 128                 RCALL   g();
 129                 SWAP    (t)
 130                 MOV     (acc, t)
 131
 132                 //voice 2:
 133                 #define tmp _
 134                 MOV     (tmp, i2)
 135                 LSL     (tmp)
 136                 LSL     (tmp)
 137                 LSL     (tmp)
 138                 MOV     (t, i1)
 139                 SWAP    (t)
 140                 ANDI    (t, 0xf)
 141                 LSR     (t)
 142                 OR      (t, tmp)
 143                 #undef tmp
 144                 EOR     (t, n)
 145                 RCALL   g();
 146                 LSR     (t)
 147                 LSR     (t)
 148                 ANDI    (t, 3)
 149                 AND     (t, s)
 150                 ADD     (acc, t)
 151
 152                 //voice 3:
 153                 MOV     (Ml, i2)
 154                 SWAP    (Ml)
 155                 ANDI    (Ml, 0xf0)
 156                 LSL     (Ml)
 157                 #define tmp _
 158                 MOV     (tmp, i1)
 159                 LSR     (tmp)
 160                 LSR     (tmp)
 161                 LSR     (tmp)
 162                 OR      (Ml, tmp)
 163                 #undef tmp
 164                 MOV     (Mh, i3)
 165                 SWAP    (Mh)
 166                 ANDI    (Mh, 0xf0)
 167                 LSL     (Mh)
 168                 #define tmp _
 169                 MOV     (tmp, i2)
 170                 LSR     (tmp)
 171                 LSR     (tmp)
 172                 LSR     (tmp)
 173                 OR      (Mh, tmp)
 174                 #undef tmp
 175                 RCALL   mod3();
 176                 ADD     (t, n)
 177                 RCALL   g();
 178                 LSR     (t)
 179                 LSR     (t)
 180                 ANDI    (t, 3)
 181                 MOV     (x, s)
 182                 INC     (x)
 183                 #define tmp _
 184                 MOV     (tmp, x)
 185                 LSR     (tmp)
 186                 LSR     (tmp)
 187                 ADD     (tmp, x)
 188                 ROR     (tmp)
 189                 LSR     (tmp)
 190                 ADD     (tmp, x)
 191                 ROR     (tmp)
 192                 LSR     (tmp)
 193                 ADD     (tmp, x)
 194                 ROR     (tmp)
 195                 LSR     (tmp)
 196                 AND     (t, tmp)
 197                 #undef tmp
 198                 ADD     (acc, t)
 199
 200                 //voice 4:
 201                 MOV     (Ml, i2)
 202                 SWAP    (Ml)
 203                 ANDI    (Ml, 0xf0)
 204                 LSL     (Ml)
 205                 LSL     (Ml)
 206                 #define tmp _
 207                 MOV     (tmp, i1)
 208                 LSR     (tmp)
 209                 LSR     (tmp)
 210                 OR      (Ml, tmp)
 211                 #undef tmp
 212                 MOV     (Mh, i3)
 213                 SWAP    (Mh)
 214                 ANDI    (Mh, 0xf0)
 215                 LSL     (Mh)
 216                 LSL     (Mh)
 217                 #define tmp _
 218                 MOV     (tmp, i2)
 219                 LSR     (tmp)
 220                 LSR     (tmp)
 221                 OR      (Mh, tmp)
 222                 #undef tmp
 223                 RCALL   mod3();
 224                 SUB     (t, n)
 225                 NEG     (t)
 226                 SUBI    (t, -8)
 227                 RCALL   g();
 228                 LSR     (t)
 229                 ANDI    (t, 3)
 230                 INC     (s)
 231                 #define tmp _
 232                 MOV     (tmp, s)
 233                 LSR     (tmp)
 234                 ADD     (tmp, s)
 235                 ROR     (tmp)
 236                 LSR     (tmp)
 237                 LSR     (tmp)
 238                 ADD     (tmp, s)
 239                 ROR     (tmp)
 240                 ADD     (tmp, s)
 241                 ROR     (tmp)
 242                 LSR     (tmp)
 243                 LSR     (tmp)
 244                 AND     (t, tmp)
 245                 #undef tmp
 246                 ADD     (acc, t)
 247
 248                 putchar(acc<<4); //TODO
 249                 SUBI    (i0, -1)
 250                 ADC     (i1, zero, !i0)
 251                 ADC     (i2, zero, !i0&&!i1)
 252                 ADC     (i3, zero, !i0&&!i1&&!i2)
 253         }
 254 }