new version
[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero; //zero register
10 u8 i0;
11 u8 i1;
12 u8 i2;
13 u8 i3;
14 u8 x;
15 u8 t;
16 u8 o;
17 u8 _;
18 #define Mh o //mod3 vars
19 #define Ml t // -"-
20 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
21 void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
24 ADD (Ml, Mh)
25 CLR (Mh)
26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
32 ANDI (Ml, 0x0f)
33 ADD (Ml, tmp)
34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
37 ANDI (Ml, 0x03)
38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
44 CPI (Ml, 3)
45 BRPL (skip)
46 SUBI (Ml, 3)
47 skip:;
48 RET
49 #undef tmp
50 }
51 void g(void) {
52 // g(i, x, t, o) -> t
53 #define tmp _
54 ANDI (t, 0x07)
55 MOV (tmp, i2)
56 ANDI (tmp, 3)
57 TST (tmp)
58 #undef tmp
59 BREQ (skip)
60 SUBI (t, -8)
61 skip:
62 t = data[t];
63 /*MOV X_hi==_, data_hi
64 MOV X_lo==t, data_lo
65 ADD X_lo, t
66 ADC X_hi, zero
67 LD t, X */
68 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
69 t >>= o; //NOTE: o == {1, 2, 4}
70 AND (t, x)
71 ANDI (t, 3)
72 RET //TODO: CALL/RET is expensive; store PC in register and RJMP, then JRMP back
73 };
74
75 int main(void) {
76 u8 n;
77 u8 s;
78 u8 acc;
79 //TODO: clear all vars/registers
80 for (;;) {
81 MOV (n, i2)
82 LSL (n)
83 LSL (n)
84 #define tmp acc
85 MOV (tmp, i1)
86 SWAP (tmp)
87 ANDI (tmp, 0x0f)
88 LSR (tmp)
89 LSR (tmp)
90 OR (n, tmp)
91 #undef tmp
92 MOV (s, i3)
93 ROR (s)
94 ROR (s)
95 ANDI (s, 0x80)
96 #define tmp acc
97 MOV (tmp, i2)
98 LSR (tmp)
99 OR (s, tmp)
100 #undef tmp
101
102 //voice 1:
103 LDI (x, 1)
104 MOV (t, n)
105 LDI (o, 4)
106 RCALL g();
107 MOV (acc, t)
108
109 //voice 2:
110 MOV (x, s)
111 #define tmp o
112 MOV (tmp, i2)
113 LSL (tmp)
114 LSL (tmp)
115 LSL (tmp)
116 MOV (t, i1)
117 SWAP (t)
118 ANDI (t, 0xf)
119 LSR (t)
120 OR (t, tmp)
121 #undef tmp
122 EOR (t, n)
123 LDI (o, 2)
124 RCALL g();
125 ADD (acc, t)
126
127 //voice 3:
128 MOV (x, s)
129 INC (x)
130 #define tmp o
131 MOV (tmp, x)
132 LSR (tmp)
133 LSR (tmp)
134 ADD (tmp, x)
135 ROR (tmp)
136 LSR (tmp)
137 ADD (tmp, x)
138 ROR (tmp)
139 LSR (tmp)
140 ADD (tmp, x)
141 ROR (tmp)
142 LSR (tmp)
143 MOV (x, tmp)
144 #undef tmp
145 MOV (Ml, i2)
146 SWAP (Ml)
147 ANDI (Ml, 0xf0)
148 LSL (Ml)
149 #define tmp Mh
150 MOV (tmp, i1)
151 LSR (tmp)
152 LSR (tmp)
153 LSR (tmp)
154 OR (Ml, tmp)
155 #undef tmp
156 MOV (Mh, i3)
157 SWAP (Mh)
158 ANDI (Mh, 0xf0)
159 LSL (Mh)
160 #define tmp _
161 MOV (tmp, i2)
162 LSR (tmp)
163 LSR (tmp)
164 LSR (tmp)
165 OR (Mh, tmp)
166 #undef tmp
167 RCALL mod3();
168 ADD (t, n)
169 LDI (o, 2)
170 RCALL g();
171 ADD (acc, t)
172
173 //voice 4:
174 MOV (x, s)
175 INC (x)
176 #define tmp o
177 MOV (tmp, x)
178 LSR (tmp)
179 ADD (tmp, x)
180 ROR (tmp)
181 LSR (tmp)
182 LSR (tmp)
183 ADD (tmp, x)
184 ROR (tmp)
185 ADD (tmp, x)
186 ROR (tmp)
187 LSR (tmp)
188 LSR (tmp)
189 MOV (x, tmp)
190 #undef tmp
191 MOV (Ml, i2)
192 SWAP (Ml)
193 ANDI (Ml, 0xf0)
194 LSL (Ml)
195 LSL (Ml)
196 #define tmp Mh
197 MOV (tmp, i1)
198 LSR (tmp)
199 LSR (tmp)
200 OR (Ml, tmp)
201 #undef tmp
202 MOV (Mh, i3)
203 SWAP (Mh)
204 ANDI (Mh, 0xf0)
205 LSL (Mh)
206 LSL (Mh)
207 #define tmp _
208 MOV (tmp, i2)
209 LSR (tmp)
210 LSR (tmp)
211 OR (Mh, tmp)
212 #undef tmp
213 RCALL mod3();
214 SUB (t, n)
215 NEG (t)
216 SUBI (t, -8)
217 LDI (o, 1)
218 RCALL g();
219 ADD (acc, t)
220
221 putchar(acc<<4); //TODO
222 SUBI (i0, -1)
223 ADC (i1, zero, !i0)
224 ADC (i2, zero, !i0&&!i1)
225 ADC (i3, zero, !i0&&!i1&&!i2)
226 }
227 }
Imprint / Impressum