foo.c

   1 #include <stdio.h>
   2 #include "fakeasm.h"
   3 typedef unsigned char u8;
   4
   5 u8 data[] = {
   6         0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
   7         0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
   8 };
   9 u8 zero;        //r16
  10 u8 acc;         //r17
  11 u8 i0;          //r18
  12 u8 i1;          //r19
  13 u8 i2;          //r20
  14 u8 i3;          //r21
  15 u8 n;           //r22
  16 u8 s;           //r23
  17 u8 _;           //r24
  18 u8 loop;        //r25
  19 u8 t;/*==Ml*/   //r26 (Xlo)
  20 u8 x;/*==Mh*/   //r27 (Xhi)
  21                 //r28
  22                 //r29
  23 /*fakestack_l*/ //r30 (Zlo)
  24 /*fakestack_h*/ //r31 (Zhi)
  25 #define Mh x //mod3 vars
  26 #define Ml t // -"-
  27 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
  28 void mod3(void) {
  29         // mod3(Mh.Ml) -> t
  30         #define tmp _
  31         ADD     (Ml, Mh)
  32         CLR     (Mh)
  33         ADC     (Mh, zero, carry) //Mh only holds the carry bit
  34         MOV     (tmp, Ml)
  35         SWAP    (tmp)
  36         ANDI    (tmp, 0x0f)
  37         SWAP    (Mh)
  38         OR      (tmp, Mh)
  39         ANDI    (Ml, 0x0f)
  40         ADD     (Ml, tmp)
  41         MOV     (tmp, Ml)
  42         LSR     (tmp)
  43         LSR     (tmp)
  44         ANDI    (Ml, 0x03)
  45         ADD     (Ml, tmp)
  46         MOV     (tmp, Ml)
  47         LSR     (tmp)
  48         LSR     (tmp)
  49         ANDI    (Ml, 0x03)
  50         ADD     (Ml, tmp)
  51         CPI     (Ml, 3)
  52         BRPL    (skip)
  53         SUBI    (Ml, 3)
  54         skip:;
  55         RET
  56         #undef tmp
  57 }
  58 void g(void) {
  59         // g(i, t) -> t
  60         // tempvars: `x` and `_`
  61         #define tmp _
  62         ANDI    (t, 0x07)
  63         MOV     (tmp, i2)
  64         ANDI    (tmp, 3)
  65         TST     (tmp)
  66         #undef tmp
  67         BREQ    (skip)
  68         SUBI    (t, -8)
  69         skip:
  70         t = data[t];
  71         /*MOV X_hi==x, data_hi
  72           MOV X_lo==t, data_lo
  73           ADD X_lo, t
  74           ADC X_hi, zero
  75           LD  t, X         */
  76         #define a1 x
  77         #define a2 _
  78         #define a0 t
  79         // start MUL -- 92 cycles :( (unrolled and skipping second bit: 76)
  80         CLR     (a2)
  81         CLR     (a1)
  82         LDI     (loop, 8)
  83         mul:
  84         SBRS    (t, 0)
  85         RJMP    (skip2)
  86         ADD     (a1, i0)
  87         ADC     (a2, i1, carry)
  88         skip2:
  89         LSR     (a2)
  90         ROR     (a1)
  91         ROR     (t)
  92         DEC     (loop)
  93         BRNE    (mul)
  94         // end MUL
  95         MOV     (t, a1)
  96         #undef a0
  97         #undef a1
  98         #undef a2
  99
 100         RET //TODO: replace CALL/RET with IJMP?
 101 };
 102
 103 int main(void) {
 104         CLR     (zero)
 105         CLR     (i0)
 106         CLR     (i1)
 107         CLR     (i2)
 108         CLR     (i3)
 109         for (;;) {
 110                 MOV     (n, i2)
 111                 LSL     (n)
 112                 LSL     (n)
 113                 #define tmp _
 114                 MOV     (tmp, i1)
 115                 SWAP    (tmp)
 116                 ANDI    (tmp, 0x0f)
 117                 LSR     (tmp)
 118                 LSR     (tmp)
 119                 OR      (n, tmp)
 120                 #undef tmp
 121                 MOV     (s, i3)
 122                 LSR     (s)
 123                 ROR     (s)
 124                 ANDI    (s, 0x80)
 125                 #define tmp _
 126                 MOV     (tmp, i2)
 127                 LSR     (tmp)
 128                 OR      (s, tmp)
 129                 #undef tmp
 130
 131                 //voice 1:
 132                 MOV     (t, n)
 133                 RCALL   g();
 134                 SWAP    (t)
 135                 ANDI    (t, 1)
 136                 MOV     (acc, t)
 137
 138                 //voice 2:
 139                 #define tmp _
 140                 MOV     (tmp, i2)
 141                 LSL     (tmp)
 142                 LSL     (tmp)
 143                 LSL     (tmp)
 144                 MOV     (t, i1)
 145                 SWAP    (t)
 146                 ANDI    (t, 0xf)
 147                 LSR     (t)
 148                 OR      (t, tmp)
 149                 #undef tmp
 150                 EOR     (t, n)
 151                 RCALL   g();
 152                 LSR     (t)
 153                 LSR     (t)
 154                 ANDI    (t, 3)
 155                 AND     (t, s)
 156                 ADD     (acc, t)
 157
 158                 //voice 3:
 159                 MOV     (Ml, i2)
 160                 SWAP    (Ml)
 161                 ANDI    (Ml, 0xf0)
 162                 LSL     (Ml)
 163                 #define tmp _
 164                 MOV     (tmp, i1)
 165                 LSR     (tmp)
 166                 LSR     (tmp)
 167                 LSR     (tmp)
 168                 OR      (Ml, tmp)
 169                 #undef tmp
 170                 MOV     (Mh, i3)
 171                 SWAP    (Mh)
 172                 ANDI    (Mh, 0xf0)
 173                 LSL     (Mh)
 174                 #define tmp _
 175                 MOV     (tmp, i2)
 176                 LSR     (tmp)
 177                 LSR     (tmp)
 178                 LSR     (tmp)
 179                 OR      (Mh, tmp)
 180                 #undef tmp
 181                 RCALL   mod3();
 182                 ADD     (t, n)
 183                 RCALL   g();
 184                 LSR     (t)
 185                 LSR     (t)
 186                 ANDI    (t, 3)
 187                 MOV     (x, s)
 188                 INC     (x)
 189                 #define tmp _
 190                 MOV     (tmp, x)
 191                 LSR     (tmp)
 192                 LSR     (tmp)
 193                 ADD     (tmp, x)
 194                 ROR     (tmp)
 195                 LSR     (tmp)
 196                 ADD     (tmp, x)
 197                 ROR     (tmp)
 198                 LSR     (tmp)
 199                 ADD     (tmp, x)
 200                 ROR     (tmp)
 201                 LSR     (tmp)
 202                 AND     (t, tmp)
 203                 #undef tmp
 204                 ADD     (acc, t)
 205
 206                 //voice 4:
 207                 MOV     (Ml, i2)
 208                 SWAP    (Ml)
 209                 ANDI    (Ml, 0xf0)
 210                 LSL     (Ml)
 211                 LSL     (Ml)
 212                 #define tmp _
 213                 MOV     (tmp, i1)
 214                 LSR     (tmp)
 215                 LSR     (tmp)
 216                 OR      (Ml, tmp)
 217                 #undef tmp
 218                 MOV     (Mh, i3)
 219                 SWAP    (Mh)
 220                 ANDI    (Mh, 0xf0)
 221                 LSL     (Mh)
 222                 LSL     (Mh)
 223                 #define tmp _
 224                 MOV     (tmp, i2)
 225                 LSR     (tmp)
 226                 LSR     (tmp)
 227                 OR      (Mh, tmp)
 228                 #undef tmp
 229                 RCALL   mod3();
 230                 SUB     (t, n)
 231                 NEG     (t)
 232                 SUBI    (t, -8)
 233                 RCALL   g();
 234                 LSR     (t)
 235                 ANDI    (t, 3)
 236                 INC     (s)
 237                 #define tmp _
 238                 MOV     (tmp, s)
 239                 LSR     (tmp)
 240                 ADD     (tmp, s)
 241                 ROR     (tmp)
 242                 LSR     (tmp)
 243                 LSR     (tmp)
 244                 ADD     (tmp, s)
 245                 ROR     (tmp)
 246                 ADD     (tmp, s)
 247                 ROR     (tmp)
 248                 LSR     (tmp)
 249                 LSR     (tmp)
 250                 AND     (t, tmp)
 251                 #undef tmp
 252                 ADD     (acc, t)
 253
 254                 putchar(acc<<4); //TODO
 255                 SUBI    (i0, -1)
 256                 ADC     (i1, zero, !i0)
 257                 ADC     (i2, zero, !i0&&!i1)
 258                 ADC     (i3, zero, !i0&&!i1&&!i2)
 259         }
 260 }