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[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero; //zero register
10 u8 i0;
11 u8 i1;
12 u8 i2;
13 u8 i3;
14 u8 x;
15 u8 t;
16 u8 o;
17 u8 _;
18 #define Mh o //mod3 vars
19 #define Ml t // -"-
20 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
21 void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
24 ADD (Ml, Mh)
25 CLR (Mh)
26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
32 ANDI (Ml, 0x0f)
33 ADD (Ml, tmp)
34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
37 ANDI (Ml, 0x03)
38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
44 CPI (Ml, 3)
45 BRPL (skip)
46 SUBI (Ml, 3)
47 skip:;
48 RET
49 #undef tmp
50 }
51 void g(void) {
52 // g(i, x, t, o) -> t
53 #define tmp _
54 ANDI (t, 0x07)
55 MOV (tmp, i2)
56 ANDI (tmp, 3)
57 TST (tmp)
58 #undef tmp
59 BREQ (skip)
60 SUBI (t, -8)
61 skip:
62 t = data[t];
63 /*MOV X_hi==_, data_hi
64 MOV X_lo==t, data_lo
65 ADD X_lo, t
66 ADC X_hi, zero
67 LD t, X */
68 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
69 t >>= o; //NOTE: o == {1, 2, 4}
70 ANDI (t, 3)
71 RET //TODO: CALL/RET is expensive; store PC in register and RJMP, then JRMP back
72 };
73
74 int main(void) {
75 u8 n;
76 u8 s;
77 u8 acc;
78 //TODO: clear all vars/registers
79 for (;;) {
80 MOV (n, i2)
81 LSL (n)
82 LSL (n)
83 #define tmp acc
84 MOV (tmp, i1)
85 SWAP (tmp)
86 ANDI (tmp, 0x0f)
87 LSR (tmp)
88 LSR (tmp)
89 OR (n, tmp)
90 #undef tmp
91 MOV (s, i3)
92 ROR (s)
93 ROR (s)
94 ANDI (s, 0x80)
95 #define tmp acc
96 MOV (tmp, i2)
97 LSR (tmp)
98 OR (s, tmp)
99 #undef tmp
100
101 //voice 1:
102 LDI (x, 1)
103 MOV (t, n)
104 LDI (o, 4)
105 RCALL g();
106 AND (t, x)
107 MOV (acc, t)
108
109 //voice 2:
110 MOV (x, s)
111 #define tmp o
112 MOV (tmp, i2)
113 LSL (tmp)
114 LSL (tmp)
115 LSL (tmp)
116 MOV (t, i1)
117 SWAP (t)
118 ANDI (t, 0xf)
119 LSR (t)
120 OR (t, tmp)
121 #undef tmp
122 EOR (t, n)
123 LDI (o, 2)
124 RCALL g();
125 AND (t, x)
126 ADD (acc, t)
127
128 //voice 3:
129 MOV (x, s)
130 INC (x)
131 #define tmp o
132 MOV (tmp, x)
133 LSR (tmp)
134 LSR (tmp)
135 ADD (tmp, x)
136 ROR (tmp)
137 LSR (tmp)
138 ADD (tmp, x)
139 ROR (tmp)
140 LSR (tmp)
141 ADD (tmp, x)
142 ROR (tmp)
143 LSR (tmp)
144 MOV (x, tmp)
145 #undef tmp
146 MOV (Ml, i2)
147 SWAP (Ml)
148 ANDI (Ml, 0xf0)
149 LSL (Ml)
150 #define tmp Mh
151 MOV (tmp, i1)
152 LSR (tmp)
153 LSR (tmp)
154 LSR (tmp)
155 OR (Ml, tmp)
156 #undef tmp
157 MOV (Mh, i3)
158 SWAP (Mh)
159 ANDI (Mh, 0xf0)
160 LSL (Mh)
161 #define tmp _
162 MOV (tmp, i2)
163 LSR (tmp)
164 LSR (tmp)
165 LSR (tmp)
166 OR (Mh, tmp)
167 #undef tmp
168 RCALL mod3();
169 ADD (t, n)
170 LDI (o, 2)
171 RCALL g();
172 AND (t, x)
173 ADD (acc, t)
174
175 //voice 4:
176 MOV (x, s)
177 INC (x)
178 #define tmp o
179 MOV (tmp, x)
180 LSR (tmp)
181 ADD (tmp, x)
182 ROR (tmp)
183 LSR (tmp)
184 LSR (tmp)
185 ADD (tmp, x)
186 ROR (tmp)
187 ADD (tmp, x)
188 ROR (tmp)
189 LSR (tmp)
190 LSR (tmp)
191 MOV (x, tmp)
192 #undef tmp
193 MOV (Ml, i2)
194 SWAP (Ml)
195 ANDI (Ml, 0xf0)
196 LSL (Ml)
197 LSL (Ml)
198 #define tmp Mh
199 MOV (tmp, i1)
200 LSR (tmp)
201 LSR (tmp)
202 OR (Ml, tmp)
203 #undef tmp
204 MOV (Mh, i3)
205 SWAP (Mh)
206 ANDI (Mh, 0xf0)
207 LSL (Mh)
208 LSL (Mh)
209 #define tmp _
210 MOV (tmp, i2)
211 LSR (tmp)
212 LSR (tmp)
213 OR (Mh, tmp)
214 #undef tmp
215 RCALL mod3();
216 SUB (t, n)
217 NEG (t)
218 SUBI (t, -8)
219 LDI (o, 1)
220 RCALL g();
221 AND (t, x)
222 ADD (acc, t)
223
224 putchar(acc<<4); //TODO
225 SUBI (i0, -1)
226 ADC (i1, zero, !i0)
227 ADC (i2, zero, !i0&&!i1)
228 ADC (i3, zero, !i0&&!i1&&!i2)
229 }
230 }
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