remove dedicated zero register (saves 4 bytes of progmem)
[Chiptunes.git] / foo.S
1 /* REGISTER NAMES */
2 #define acc r16
3 #define i0 r17
4 #define i1 r18
5 #define i2 r19
6 #define i3 r20
7 #define n r21
8 #define s r22
9 #define t r23 //==Ml
10 ; r24
11 ; r25
12 #define x r26 //==Xlo==Mh
13 #define _ r27 //==Xhi
14 ; r28
15 ; r29
16 ; r30 Zlo
17 ; r31 Zhi
18 ; aliases:
19 #define Xlo r26
20 #define Xhi r27
21 #define Ml r24 //mod3 vars
22 #define Mh r26 // -"-
23
24 /* I/O REGISTERS */
25 OCR0AL = 0x26
26 DDRB = 0x01
27 PORTB = 0x02
28 PUEB = 0x03
29 SPL = 0x3D
30 SPH = 0x3E
31 CCP = 0x3C
32 CLKPSR = 0x36
33 WDTCSR = 0x31
34 SMCR = 0x3A
35 TCCR0A = 0x2E
36 TCCR0B = 0x2D
37 TIMSK0 = 0x2B
38 TIFR0 = 0x2A
39
40 .section .data
41 notes:
42 .byte 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58
43 .byte 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
44
45 .section .text
46 .org 0x0000 ; RESET interrupt
47 RJMP main
48 .org 0x0008 ; TIM0_OVF interrupt
49 RJMP sample
50
51 mod3: ; mod3(Mh.Ml) -> t
52 #define tmp _
53 ADD Ml, Mh
54 CLR Mh
55 ADC Mh, Mh ; store carry in Mh
56 MOV tmp, Ml
57 SWAP tmp
58 ANDI tmp, 0x0f
59 SWAP Mh
60 OR tmp, Mh
61 ANDI Ml, 0x0f
62 ADD Ml, tmp
63 MOV tmp, Ml
64 LSR tmp
65 LSR tmp
66 ANDI Ml, 0x03
67 ADD Ml, tmp
68 MOV tmp, Ml
69 LSR tmp
70 LSR tmp
71 ANDI Ml, 0x03
72 ADD Ml, tmp
73 CPI Ml, 3
74 BRPL skip
75 SUBI Ml, 3
76 skip:
77 RET
78 #undef tmp
79
80 ; definitions to mul-tree readable:
81 #define a1 x
82 #define a2 _
83 .macro always _bit ; nop; for when a test() is not necessary (see tree)
84 .endm
85 .macro never _bit ; nop; for when a test() is not necessary (see tree)
86 .endm
87 .macro test _bit,_jmpto
88 SBRC t, \_bit
89 RJMP \_jmpto
90 .endm
91 .macro i_test _bit,_jmpto ; inverted test (for reordered 0x8_)
92 SBRS t, \_bit
93 RJMP \_jmpto
94 .endm
95 .macro shift16
96 LSR a2
97 ROR a1
98 .endm
99 .macro shift8 ; top three bits don't need to be corrrect, so save cycles by not carrying
100 LSR a1
101 .endm
102 .macro shift0 ; nop; last shift is common
103 .endm
104 .macro add16
105 ADD a1, i0
106 ADC a2, i1
107 .endm
108 .macro add8 ; ditto with carrying
109 ADD a1, i0
110 .endm
111 #undef a2
112 #undef a1
113
114 g: ; g(i, t) -> t
115 #define a1 x
116 #define a2 _
117 CLR a2
118 CLR a1
119
120 #define tmp _
121 #define zero a1
122 ANDI t, 0x07
123 MOV tmp, i2
124 ANDI tmp, 3
125 CPSE tmp, zero
126 SUBI t, -8
127 #undef zero
128 #undef tmp
129
130 ;TODO: check correctness!
131 LDI Xhi, hi8(notes) ; hi(notes) always zero, but still need to clear the register
132 LDI Xlo, lo8(notes)
133 ADD Xlo, t ; NOTE: can't overflow, since RAMEND == 0x5F
134 LD t, X
135
136 /* decision tree multiplication saves cycles and (hopefully) reduces code size
137 _xxx?
138 / \
139 _xx?0 _xx1?
140 | |
141 _x?00 _x?01
142 / \ / \
143 _?000 _?100 _?001 _?101
144 / \ / \ | / \
145 _0000 _1000 _0100 _1100 _1001 _0101 _1101
146 | | | | | | |
147 ... ... ... ... ... ... ...
148 | | | | | | |
149 B0 58 84 8C 69 75 9D */
150 test 0, m____1
151 m____0: shift16
152 never 1
153 m___00: shift16
154 test 2, m__100
155 m__000: shift16
156 test 3, m_1000
157 m_0000: shift16
158 always 4
159 add16 $ shift16
160 always 5
161 add8 $ shift8
162 never 6
163 shift8
164 always 7
165 add8 $ shift0
166 RJMP end_mul ; calc'd 0xb0
167
168 m_1000: add16 $ shift16
169 always 4
170 add16 $ shift16
171 never 5
172 shift8
173 always 6
174 add8 $ shift8
175 never 7
176 shift0
177 RJMP end_mul ; calc'd 0x58
178
179 m__100: add16 $ shift16
180 i_test 3, m_0100
181 m_1100: add16
182 m_0100: shift16
183 never 4
184 shift16
185 never 5
186 shift8
187 never 6
188 shift8
189 always 7
190 add8 $ shift0
191 RJMP end_mul ; calc'd 0x8c / 0x84
192
193 m____1: add16 $ shift16
194 never 1
195 m___01: shift16
196 test 2, m__101
197 m__001: shift16
198 always 3
199 m_1001: add16 $ shift16
200 never 4
201 shift16
202 always 5
203 add8 $ shift8
204 always 6
205 add8 $ shift8
206 never 7
207 shift0
208 RJMP end_mul ; calc'd 0x69
209
210 m__101: add16 $ shift16
211 test 3, m_1101
212 m_0101: shift16
213 always 4
214 add16 $ shift16
215 always 5
216 add8 $ shift8
217 always 6
218 add8 $ shift8
219 never 7
220 shift0
221 RJMP end_mul ; calc'd 0x75
222
223 m_1101: add16 $ shift16
224 always 4
225 add16 $ shift16
226 never 5
227 shift8
228 never 6
229 shift8
230 always 7
231 add8 $ shift0
232 ; calc'd 0x9d
233
234 end_mul:
235 LSR a1 ;final shift is a common operation for all
236
237 MOV t, a1 ;;TODO: use a1 in main() directly
238 #undef a1
239 #undef a2
240 RET ; TODO: replace CALL/RET with IJMP?
241
242 main: ; setup routine
243 CLR i0
244 CLR i1
245 CLR i2
246 CLR i3
247 CLR acc ; we output a dummy sample before the actual first one
248
249 #define zero i0
250 #define one _
251 LDI one, 1
252 LDI x, 0x5f ; RAMEND
253 OUT SPL, x ; init stack ptr
254 OUT SPH, zero ; -"-
255 OUT PUEB, zero ; disable pullups
256 LDI x, 0x05
257 OUT DDRB, x ; PORTB0:pwm, PORTB2:debug
258 LDI x, 0xd8
259 OUT CCP, x ; change protected ioregs
260 OUT CLKPSR, one ; clock prescaler 1/2 (4Mhz)
261 OUT WDTCSR, zero; turn off watchdog ;;TODO: incomplete - see datasheet pg48
262 ; OUT SMCR, 2 ; sleep mode 'power down' ('idle' (default) has faster response time)
263
264 ;set timer/counter0 to 8bit fastpwm, non-inverting, no prescaler
265 LDI x, 0x81
266 OUT TCCR0A, x
267 LDI x, 0x09
268 OUT TCCR0B, x
269 OUT TIMSK0, one ; enable tim0_ovf
270 OUT TIFR0, one ; TODO: why?
271 SEI
272 #undef one
273 #undef zero
274 RJMP sample
275
276 loop:
277 SLEEP ; wait for interrupt
278 RJMP loop
279
280 sample:
281 ; potential TODO: softcounter in r25 to only update duty cicle every n iterations
282 ; potential TODO: save/restore status register (SREG=0x3f) (only if something in mainloop)
283
284 OUT OCR0AL, acc ; start by outputting a sample, because routine has variable runtime
285 SBI PORTB, 2 ; to measure runtime
286
287 MOV n, i2
288 LSL n
289 LSL n
290 #define tmp _
291 MOV tmp, i1
292 SWAP tmp
293 ANDI tmp, 0x0f
294 LSR tmp
295 LSR tmp
296 OR n, tmp
297 #undef tmp
298 MOV s, i3
299 LSR s
300 ROR s
301 ANDI s, 0x80
302 #define tmp _
303 MOV tmp, i2
304 LSR tmp
305 OR s, tmp
306 #undef tmp
307
308 ; voice 1:
309 MOV t, n
310 RCALL g
311 SWAP t
312 ANDI t, 1
313 MOV acc, t
314
315 ; voice 2:
316 #define tmp _
317 MOV tmp, i2
318 LSL tmp
319 LSL tmp
320 LSL tmp
321 MOV t, i1
322 SWAP t
323 ANDI t, 0xf
324 LSR t
325 OR t, tmp
326 #undef tmp
327 EOR t, n
328 RCALL g
329 LSR t
330 LSR t
331 ANDI t, 3
332 AND t, s
333 ADD acc, t
334
335 ; voice 3:
336 MOV Ml, i2
337 SWAP Ml
338 ANDI Ml, 0xf0
339 LSL Ml
340 #define tmp _
341 MOV tmp, i1
342 LSR tmp
343 LSR tmp
344 LSR tmp
345 OR Ml, tmp
346 #undef tmp
347 MOV Mh, i3
348 SWAP Mh
349 ANDI Mh, 0xf0
350 LSL Mh
351 #define tmp _
352 MOV tmp, i2
353 LSR tmp
354 LSR tmp
355 LSR tmp
356 OR Mh, tmp
357 #undef tmp
358 RCALL mod3
359 ADD t, n
360 RCALL g
361 LSR t
362 LSR t
363 ANDI t, 3
364 MOV x, s
365 INC x
366 #define tmp _
367 MOV tmp, x
368 LSR tmp
369 LSR tmp
370 ADD tmp, x
371 ROR tmp
372 LSR tmp
373 ADD tmp, x
374 ROR tmp
375 LSR tmp
376 ADD tmp, x
377 ROR tmp
378 LSR tmp
379 AND t, tmp
380 #undef tmp
381 ADD acc, t
382
383 ; voice 4:
384 MOV Ml, i2
385 SWAP Ml
386 ANDI Ml, 0xf0
387 LSL Ml
388 LSL Ml
389 #define tmp _
390 MOV tmp, i1
391 LSR tmp
392 LSR tmp
393 OR Ml, tmp
394 #undef tmp
395 MOV Mh, i3
396 SWAP Mh
397 ANDI Mh, 0xf0
398 LSL Mh
399 LSL Mh
400 #define tmp _
401 MOV tmp, i2
402 LSR tmp
403 LSR tmp
404 OR Mh, tmp
405 #undef tmp
406 RCALL mod3
407 SUB t, n
408 NEG t
409 SUBI t, -8
410 RCALL g
411 LSR t
412 ANDI t, 3
413 INC s
414 #define tmp _
415 MOV tmp, s
416 LSR tmp
417 ADD tmp, s
418 ROR tmp
419 LSR tmp
420 LSR tmp
421 ADD tmp, s
422 ROR tmp
423 ADD tmp, s
424 ROR tmp
425 LSR tmp
426 LSR tmp
427 AND t, tmp
428 #undef tmp
429 ADD acc, t
430
431 SWAP acc ; acc<<4, to be passed to OCR0AL
432
433 SUBI i0, -1
434 SBCI i1, -1
435 SBCI i2, -1
436 SBCI i3, -1
437
438 CBI PORTB, 2 ; end runtime measurement
439 ;TODO: to reduce jitter: clear pending tim0_ovf (TIFR0[TOV0] <- 1) ?
440 RETI ; reenables interrupts
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