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[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero; //r16
10 u8 acc; //r17
11 u8 i0; //r18
12 u8 i1; //r19
13 u8 i2; //r20
14 u8 i3; //r21
15 u8 n; //r22
16 u8 s; //r23
17 u8 _; //r24
18 //r25
19 u8 t;/*==Ml*/ //r26 (Xlo)
20 u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23 /*fakestack_l*/ //r30 (Zlo)
24 /*fakestack_h*/ //r31 (Zhi)
25 #define Mh x //mod3 vars
26 #define Ml t // -"-
27 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
28 void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
31 ADD (Ml, Mh)
32 CLR (Mh)
33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
39 ANDI (Ml, 0x0f)
40 ADD (Ml, tmp)
41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
44 ANDI (Ml, 0x03)
45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
51 CPI (Ml, 3)
52 BRPL (skip)
53 SUBI (Ml, 3)
54 skip:;
55 RET
56 #undef tmp
57 }
58 void g(void) {
59 // g(i, t) -> t
60 // tempvars: `x` and `_`
61 #define tmp _
62 ANDI (t, 0x07)
63 MOV (tmp, i2)
64 ANDI (tmp, 3)
65 TST (tmp)
66 #undef tmp
67 BREQ (skip)
68 SUBI (t, -8)
69 skip:
70 t = data[t];
71 /*MOV X_hi==x, data_hi
72 MOV X_lo==t, data_lo
73 ADD X_lo, t
74 ADC X_hi, zero
75 LD t, X */
76 //t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
77
78 #define a1 x
79 #define a2 _
80 a2 = 0;
81 a1 = 0;
82 #define a0 t
83
84 for (u8 loop = 0; loop < 8; loop++) { //Note: t&2 always zero
85 SBRS (t, 0)
86 goto skip2;
87 if (t & 1) {
88 ADD (a1, i0)
89 ADC (a2, i1, carry)
90 }
91 skip2:
92 LSR (a2)
93 ROR (a1)
94 ROR (t)
95 }
96 t = a1;
97 #undef a0
98
99 RET //TODO: replace CALL/RET with IJMP?
100 };
101
102 int main(void) {
103 CLR (zero)
104 CLR (i0)
105 CLR (i1)
106 CLR (i2)
107 CLR (i3)
108 for (;;) {
109 MOV (n, i2)
110 LSL (n)
111 LSL (n)
112 #define tmp _
113 MOV (tmp, i1)
114 SWAP (tmp)
115 ANDI (tmp, 0x0f)
116 LSR (tmp)
117 LSR (tmp)
118 OR (n, tmp)
119 #undef tmp
120 MOV (s, i3)
121 LSR (s)
122 ROR (s)
123 ANDI (s, 0x80)
124 #define tmp _
125 MOV (tmp, i2)
126 LSR (tmp)
127 OR (s, tmp)
128 #undef tmp
129
130 //voice 1:
131 MOV (t, n)
132 RCALL g();
133 SWAP (t)
134 ANDI (t, 1)
135 MOV (acc, t)
136
137 //voice 2:
138 #define tmp _
139 MOV (tmp, i2)
140 LSL (tmp)
141 LSL (tmp)
142 LSL (tmp)
143 MOV (t, i1)
144 SWAP (t)
145 ANDI (t, 0xf)
146 LSR (t)
147 OR (t, tmp)
148 #undef tmp
149 EOR (t, n)
150 RCALL g();
151 LSR (t)
152 LSR (t)
153 ANDI (t, 3)
154 AND (t, s)
155 ADD (acc, t)
156
157 //voice 3:
158 MOV (Ml, i2)
159 SWAP (Ml)
160 ANDI (Ml, 0xf0)
161 LSL (Ml)
162 #define tmp _
163 MOV (tmp, i1)
164 LSR (tmp)
165 LSR (tmp)
166 LSR (tmp)
167 OR (Ml, tmp)
168 #undef tmp
169 MOV (Mh, i3)
170 SWAP (Mh)
171 ANDI (Mh, 0xf0)
172 LSL (Mh)
173 #define tmp _
174 MOV (tmp, i2)
175 LSR (tmp)
176 LSR (tmp)
177 LSR (tmp)
178 OR (Mh, tmp)
179 #undef tmp
180 RCALL mod3();
181 ADD (t, n)
182 RCALL g();
183 LSR (t)
184 LSR (t)
185 ANDI (t, 3)
186 MOV (x, s)
187 INC (x)
188 #define tmp _
189 MOV (tmp, x)
190 LSR (tmp)
191 LSR (tmp)
192 ADD (tmp, x)
193 ROR (tmp)
194 LSR (tmp)
195 ADD (tmp, x)
196 ROR (tmp)
197 LSR (tmp)
198 ADD (tmp, x)
199 ROR (tmp)
200 LSR (tmp)
201 AND (t, tmp)
202 #undef tmp
203 ADD (acc, t)
204
205 //voice 4:
206 MOV (Ml, i2)
207 SWAP (Ml)
208 ANDI (Ml, 0xf0)
209 LSL (Ml)
210 LSL (Ml)
211 #define tmp _
212 MOV (tmp, i1)
213 LSR (tmp)
214 LSR (tmp)
215 OR (Ml, tmp)
216 #undef tmp
217 MOV (Mh, i3)
218 SWAP (Mh)
219 ANDI (Mh, 0xf0)
220 LSL (Mh)
221 LSL (Mh)
222 #define tmp _
223 MOV (tmp, i2)
224 LSR (tmp)
225 LSR (tmp)
226 OR (Mh, tmp)
227 #undef tmp
228 RCALL mod3();
229 SUB (t, n)
230 NEG (t)
231 SUBI (t, -8)
232 RCALL g();
233 LSR (t)
234 ANDI (t, 3)
235 INC (s)
236 #define tmp _
237 MOV (tmp, s)
238 LSR (tmp)
239 ADD (tmp, s)
240 ROR (tmp)
241 LSR (tmp)
242 LSR (tmp)
243 ADD (tmp, s)
244 ROR (tmp)
245 ADD (tmp, s)
246 ROR (tmp)
247 LSR (tmp)
248 LSR (tmp)
249 AND (t, tmp)
250 #undef tmp
251 ADD (acc, t)
252
253 putchar(acc<<4); //TODO
254 SUBI (i0, -1)
255 ADC (i1, zero, !i0)
256 ADC (i2, zero, !i0&&!i1)
257 ADC (i3, zero, !i0&&!i1&&!i2)
258 }
259 }
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