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[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero; //zero register
10 u8 i0;
11 u8 i1;
12 u8 i2;
13 u8 i3;
14 u8 x;
15 u8 t;
16 u8 o;
17 u8 _;
18 void g(void) {
19 // g(i, x, t, o) -> t
20 #define tmp _
21 ANDI (t, 0x07)
22 MOV (tmp, i2)
23 ANDI (tmp, 3)
24 TST (tmp)
25 #undef tmp
26 BREQ (skip)
27 SUBI (t, -8)
28 skip:
29 t = data[t];
30 /*MOV X_hi==_, data_hi
31 MOV X_lo==t, data_lo
32 ADD X_lo, t
33 ADC X_hi, zero
34 LD t, X */
35 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
36 t >>= o; //NOTE: o == {1, 2, 4}
37 AND (t, x)
38 ANDI (t, 3)
39 RET
40 };
41
42 int main(void) {
43 u8 n;
44 u8 s;
45 u8 acc;
46 //TODO: clear all vars/registers
47 for (;;) {
48 MOV (n, i2)
49 LSL (n)
50 LSL (n)
51 #define tmp acc
52 MOV (tmp, i1)
53 SWAP (tmp)
54 ANDI (tmp, 0x0f)
55 LSR (tmp)
56 LSR (tmp)
57 OR (n, tmp)
58 #undef tmp
59 MOV (s, i3)
60 ROR (s)
61 ROR (s)
62 ANDI (s, 0x80)
63 #define tmp acc
64 MOV (tmp, i2)
65 LSR (tmp)
66 OR (s, tmp)
67 #undef tmp
68
69 //voice 1:
70 LDI (x, 1)
71 MOV (t, n)
72 LDI (o, 4)
73 RCALL g();
74 MOV (acc, t)
75
76 //voice 2:
77 MOV (x, s)
78 #define tmp o
79 MOV (tmp, i2)
80 LSL (tmp)
81 LSL (tmp)
82 LSL (tmp)
83 MOV (t, i1)
84 SWAP (t)
85 ANDI (t, 0xf)
86 LSR (t)
87 OR (t, tmp)
88 #undef tmp
89 EOR (t, n)
90 LDI (o, 2)
91 RCALL g();
92 ADD (acc, t)
93
94 //voice 3:
95 MOV (x, s)
96 INC (x)
97 #define tmp o
98 MOV (tmp, x)
99 LSR (tmp)
100 LSR (tmp)
101 ADD (tmp, x)
102 ROR (tmp)
103 LSR (tmp)
104 ADD (tmp, x)
105 ROR (tmp)
106 LSR (tmp)
107 ADD (tmp, x)
108 ROR (tmp)
109 LSR (tmp)
110 MOV (x, tmp)
111 #undef tmp
112 t = ((i3&0x01)<<13 | i2<<5 | i1>>3) % 3; //TODO
113 ADD (t, n)
114 LDI (o, 2)
115 RCALL g();
116 ADD (acc, t)
117
118 //voice 4:
119 MOV (x, s)
120 INC (x)
121 #define tmp o
122 MOV (tmp, x)
123 LSR (tmp)
124 ADD (tmp, x)
125 ROR (tmp)
126 LSR (tmp)
127 LSR (tmp)
128 ADD (tmp, x)
129 ROR (tmp)
130 ADD (tmp, x)
131 ROR (tmp)
132 LSR (tmp)
133 LSR (tmp)
134 MOV (x, tmp)
135 #undef tmp
136 t = ((i3&0x01)<<14 | i2<<6 | i1>>2) % 3; //TODO
137 SUB (t, n)
138 NEG (t)
139 SUBI (t, -8)
140 LDI (o, 1)
141 RCALL g();
142 ADD (acc, t)
143
144 putchar(acc<<4); //TODO
145 SUBI (i0, -1)
146 ADC (i1, zero, !i0)
147 ADC (i2, zero, !i0&&!i1)
148 ADC (i3, zero, !i0&&!i1&&!i2)
149 }
150 }
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