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[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero; //zero register
10 u8 i0;
11 u8 i1;
12 u8 i2;
13 u8 i3;
14 u8 t;
15 u8 x;
16 u8 _;
17 #define Mh x //mod3 vars
18 #define Ml t // -"-
19 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
20 void mod3(void) {
21 // mod3(Mh.Ml) -> t
22 #define tmp _
23 ADD (Ml, Mh)
24 CLR (Mh)
25 ADC (Mh, zero, carry) //Mh only holds the carry bit
26 MOV (tmp, Ml)
27 SWAP (tmp)
28 ANDI (tmp, 0x0f)
29 SWAP (Mh)
30 OR (tmp, Mh)
31 ANDI (Ml, 0x0f)
32 ADD (Ml, tmp)
33 MOV (tmp, Ml)
34 LSR (tmp)
35 LSR (tmp)
36 ANDI (Ml, 0x03)
37 ADD (Ml, tmp)
38 MOV (tmp, Ml)
39 LSR (tmp)
40 LSR (tmp)
41 ANDI (Ml, 0x03)
42 ADD (Ml, tmp)
43 CPI (Ml, 3)
44 BRPL (skip)
45 SUBI (Ml, 3)
46 skip:;
47 RET
48 #undef tmp
49 }
50 void g(void) {
51 // g(i, t) -> t
52 // tempvars: `x` and `_`
53 #define tmp _
54 ANDI (t, 0x07)
55 MOV (tmp, i2)
56 ANDI (tmp, 3)
57 TST (tmp)
58 #undef tmp
59 BREQ (skip)
60 SUBI (t, -8)
61 skip:
62 t = data[t];
63 /*MOV X_hi==_, data_hi
64 MOV X_lo==t, data_lo
65 ADD X_lo, t
66 ADC X_hi, zero
67 LD t, X */
68 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
69 RET //TODO: CALL/RET is expensive; store next-instruction-position in Z register and RJMP, then JRMP back (maybe unnecessary, since timer might need stack anyways)
70 };
71
72 int main(void) {
73 u8 n;
74 u8 s;
75 u8 acc;
76 //TODO: clear all vars/registers
77 for (;;) {
78 MOV (n, i2)
79 LSL (n)
80 LSL (n)
81 #define tmp acc
82 MOV (tmp, i1)
83 SWAP (tmp)
84 ANDI (tmp, 0x0f)
85 LSR (tmp)
86 LSR (tmp)
87 OR (n, tmp)
88 #undef tmp
89 MOV (s, i3)
90 ROR (s)
91 ROR (s)
92 ANDI (s, 0x80)
93 #define tmp acc
94 MOV (tmp, i2)
95 LSR (tmp)
96 OR (s, tmp)
97 #undef tmp
98
99 //voice 1:
100 MOV (t, n)
101 RCALL g();
102 SWAP (t)
103 ANDI (t, 0x0f)
104 ANDI (t, 1)
105 MOV (acc, t)
106
107 //voice 2:
108 #define tmp _
109 MOV (tmp, i2)
110 LSL (tmp)
111 LSL (tmp)
112 LSL (tmp)
113 MOV (t, i1)
114 SWAP (t)
115 ANDI (t, 0xf)
116 LSR (t)
117 OR (t, tmp)
118 #undef tmp
119 EOR (t, n)
120 RCALL g();
121 LSR (t)
122 LSR (t)
123 ANDI (t, 3)
124 AND (t, s)
125 ADD (acc, t)
126
127 //voice 3:
128 MOV (Ml, i2)
129 SWAP (Ml)
130 ANDI (Ml, 0xf0)
131 LSL (Ml)
132 #define tmp Mh
133 MOV (tmp, i1)
134 LSR (tmp)
135 LSR (tmp)
136 LSR (tmp)
137 OR (Ml, tmp)
138 #undef tmp
139 MOV (Mh, i3)
140 SWAP (Mh)
141 ANDI (Mh, 0xf0)
142 LSL (Mh)
143 #define tmp _
144 MOV (tmp, i2)
145 LSR (tmp)
146 LSR (tmp)
147 LSR (tmp)
148 OR (Mh, tmp)
149 #undef tmp
150 RCALL mod3();
151 ADD (t, n)
152 RCALL g();
153 LSR (t)
154 LSR (t)
155 ANDI (t, 3)
156 MOV (x, s)
157 INC (x)
158 #define tmp _
159 MOV (tmp, x)
160 LSR (tmp)
161 LSR (tmp)
162 ADD (tmp, x)
163 ROR (tmp)
164 LSR (tmp)
165 ADD (tmp, x)
166 ROR (tmp)
167 LSR (tmp)
168 ADD (tmp, x)
169 ROR (tmp)
170 LSR (tmp)
171 MOV (x, tmp)
172 #undef tmp
173 AND (t, x)
174 ADD (acc, t)
175
176 //voice 4:
177 MOV (Ml, i2)
178 SWAP (Ml)
179 ANDI (Ml, 0xf0)
180 LSL (Ml)
181 LSL (Ml)
182 #define tmp Mh
183 MOV (tmp, i1)
184 LSR (tmp)
185 LSR (tmp)
186 OR (Ml, tmp)
187 #undef tmp
188 MOV (Mh, i3)
189 SWAP (Mh)
190 ANDI (Mh, 0xf0)
191 LSL (Mh)
192 LSL (Mh)
193 #define tmp _
194 MOV (tmp, i2)
195 LSR (tmp)
196 LSR (tmp)
197 OR (Mh, tmp)
198 #undef tmp
199 RCALL mod3();
200 SUB (t, n)
201 NEG (t)
202 SUBI (t, -8)
203 RCALL g();
204 LSR (t)
205 ANDI (t, 3)
206 MOV (x, s)
207 INC (x)
208 #define tmp _
209 MOV (tmp, x)
210 LSR (tmp)
211 ADD (tmp, x)
212 ROR (tmp)
213 LSR (tmp)
214 LSR (tmp)
215 ADD (tmp, x)
216 ROR (tmp)
217 ADD (tmp, x)
218 ROR (tmp)
219 LSR (tmp)
220 LSR (tmp)
221 MOV (x, tmp)
222 #undef tmp
223 AND (t, x)
224 ADD (acc, t)
225
226 putchar(acc<<4); //TODO
227 SUBI (i0, -1)
228 ADC (i1, zero, !i0)
229 ADC (i2, zero, !i0&&!i1)
230 ADC (i3, zero, !i0&&!i1&&!i2)
231 }
232 }
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