c5b7081881df605ac0c5587aa8cb523402f0b3e9
[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero; //zero register
10 u8 i0;
11 u8 i1;
12 u8 i2;
13 u8 i3;
14 u8 x;
15 u8 t;
16 u8 o;
17 u8 _;
18 #define Mh o //mod3 vars
19 #define Ml t // -"-
20 void mod3(void) { //avail: t, o _
21 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
22 unsigned short a = ((Mh) + (Ml)) &0x1ff;
23 Mh = a>>8; //1 bit
24 Ml = a;
25 Ml = (Mh<<4|Ml>>4) + (Ml & 0xF);
26 Ml = (Ml >> 2) + (Ml & 0x3);
27 Ml = (Ml >> 2) + (Ml & 0x3);
28 if (Ml > 2) Ml = Ml - 3;
29 }
30 void g(void) {
31 // g(i, x, t, o) -> t
32 #define tmp _
33 ANDI (t, 0x07)
34 MOV (tmp, i2)
35 ANDI (tmp, 3)
36 TST (tmp)
37 #undef tmp
38 BREQ (skip)
39 SUBI (t, -8)
40 skip:
41 t = data[t];
42 /*MOV X_hi==_, data_hi
43 MOV X_lo==t, data_lo
44 ADD X_lo, t
45 ADC X_hi, zero
46 LD t, X */
47 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
48 t >>= o; //NOTE: o == {1, 2, 4}
49 AND (t, x)
50 ANDI (t, 3)
51 RET
52 };
53
54 int main(void) {
55 u8 n;
56 u8 s;
57 u8 acc;
58 //TODO: clear all vars/registers
59 for (;;) {
60 MOV (n, i2)
61 LSL (n)
62 LSL (n)
63 #define tmp acc
64 MOV (tmp, i1)
65 SWAP (tmp)
66 ANDI (tmp, 0x0f)
67 LSR (tmp)
68 LSR (tmp)
69 OR (n, tmp)
70 #undef tmp
71 MOV (s, i3)
72 ROR (s)
73 ROR (s)
74 ANDI (s, 0x80)
75 #define tmp acc
76 MOV (tmp, i2)
77 LSR (tmp)
78 OR (s, tmp)
79 #undef tmp
80
81 //voice 1:
82 LDI (x, 1)
83 MOV (t, n)
84 LDI (o, 4)
85 RCALL g();
86 MOV (acc, t)
87
88 //voice 2:
89 MOV (x, s)
90 #define tmp o
91 MOV (tmp, i2)
92 LSL (tmp)
93 LSL (tmp)
94 LSL (tmp)
95 MOV (t, i1)
96 SWAP (t)
97 ANDI (t, 0xf)
98 LSR (t)
99 OR (t, tmp)
100 #undef tmp
101 EOR (t, n)
102 LDI (o, 2)
103 RCALL g();
104 ADD (acc, t)
105
106 //voice 3:
107 MOV (x, s)
108 INC (x)
109 #define tmp o
110 MOV (tmp, x)
111 LSR (tmp)
112 LSR (tmp)
113 ADD (tmp, x)
114 ROR (tmp)
115 LSR (tmp)
116 ADD (tmp, x)
117 ROR (tmp)
118 LSR (tmp)
119 ADD (tmp, x)
120 ROR (tmp)
121 LSR (tmp)
122 MOV (x, tmp)
123 #undef tmp
124 Ml = i2<<5 | i1>>3;
125 Mh = i3<<5 | i2>>3;
126 RCALL mod3();
127 ADD (t, n)
128 LDI (o, 2)
129 RCALL g();
130 ADD (acc, t)
131
132 //voice 4:
133 MOV (x, s)
134 INC (x)
135 #define tmp o
136 MOV (tmp, x)
137 LSR (tmp)
138 ADD (tmp, x)
139 ROR (tmp)
140 LSR (tmp)
141 LSR (tmp)
142 ADD (tmp, x)
143 ROR (tmp)
144 ADD (tmp, x)
145 ROR (tmp)
146 LSR (tmp)
147 LSR (tmp)
148 MOV (x, tmp)
149 #undef tmp
150 Ml = i2<<6 | i1>>2;
151 Mh = i3<<6 | i2>>2;
152 RCALL mod3();
153 SUB (t, n)
154 NEG (t)
155 SUBI (t, -8)
156 LDI (o, 1)
157 RCALL g();
158 ADD (acc, t)
159
160 putchar(acc<<4); //TODO
161 SUBI (i0, -1)
162 ADC (i1, zero, !i0)
163 ADC (i2, zero, !i0&&!i1)
164 ADC (i3, zero, !i0&&!i1&&!i2)
165 }
166 }
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