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[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero; //zero register
10 u8 i0;
11 u8 i1;
12 u8 i2;
13 u8 i3;
14 u8 x;
15 u8 t;
16 u8 o;
17 u8 _;
18 #define Mh o //mod3 vars
19 #define Ml t // -"-
20 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
21 void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
24 ADD (Ml, Mh)
25 CLR (Mh)
26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
32 ANDI (Ml, 0x0f)
33 ADD (Ml, tmp)
34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
37 ANDI (Ml, 0x03)
38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
44 CPI (Ml, 3)
45 BRPL (skip)
46 SUBI (Ml, 3)
47 skip:;
48 RET
49 #undef tmp
50 }
51 void g(void) {
52 // g(i, x, t, o) -> t
53 #define tmp _
54 ANDI (t, 0x07)
55 MOV (tmp, i2)
56 ANDI (tmp, 3)
57 TST (tmp)
58 #undef tmp
59 BREQ (skip)
60 SUBI (t, -8)
61 skip:
62 t = data[t];
63 /*MOV X_hi==_, data_hi
64 MOV X_lo==t, data_lo
65 ADD X_lo, t
66 ADC X_hi, zero
67 LD t, X */
68 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
69 t >>= o; //NOTE: o == {1, 2, 4}
70 ANDI (t, 3)
71 RET //TODO: CALL/RET is expensive; store PC in register and RJMP, then JRMP back
72 };
73
74 int main(void) {
75 u8 n;
76 u8 s;
77 u8 acc;
78 //TODO: clear all vars/registers
79 for (;;) {
80 MOV (n, i2)
81 LSL (n)
82 LSL (n)
83 #define tmp acc
84 MOV (tmp, i1)
85 SWAP (tmp)
86 ANDI (tmp, 0x0f)
87 LSR (tmp)
88 LSR (tmp)
89 OR (n, tmp)
90 #undef tmp
91 MOV (s, i3)
92 ROR (s)
93 ROR (s)
94 ANDI (s, 0x80)
95 #define tmp acc
96 MOV (tmp, i2)
97 LSR (tmp)
98 OR (s, tmp)
99 #undef tmp
100
101 //voice 1:
102 MOV (t, n)
103 LDI (o, 4)
104 RCALL g();
105 ANDI (t, 1)
106 MOV (acc, t)
107
108 //voice 2:
109 #define tmp o
110 MOV (tmp, i2)
111 LSL (tmp)
112 LSL (tmp)
113 LSL (tmp)
114 MOV (t, i1)
115 SWAP (t)
116 ANDI (t, 0xf)
117 LSR (t)
118 OR (t, tmp)
119 #undef tmp
120 EOR (t, n)
121 LDI (o, 2)
122 RCALL g();
123 AND (t, s)
124 ADD (acc, t)
125
126 //voice 3:
127 MOV (Ml, i2)
128 SWAP (Ml)
129 ANDI (Ml, 0xf0)
130 LSL (Ml)
131 #define tmp Mh
132 MOV (tmp, i1)
133 LSR (tmp)
134 LSR (tmp)
135 LSR (tmp)
136 OR (Ml, tmp)
137 #undef tmp
138 MOV (Mh, i3)
139 SWAP (Mh)
140 ANDI (Mh, 0xf0)
141 LSL (Mh)
142 #define tmp _
143 MOV (tmp, i2)
144 LSR (tmp)
145 LSR (tmp)
146 LSR (tmp)
147 OR (Mh, tmp)
148 #undef tmp
149 RCALL mod3();
150 ADD (t, n)
151 LDI (o, 2)
152 RCALL g();
153 MOV (x, s)
154 INC (x)
155 #define tmp o
156 MOV (tmp, x)
157 LSR (tmp)
158 LSR (tmp)
159 ADD (tmp, x)
160 ROR (tmp)
161 LSR (tmp)
162 ADD (tmp, x)
163 ROR (tmp)
164 LSR (tmp)
165 ADD (tmp, x)
166 ROR (tmp)
167 LSR (tmp)
168 MOV (x, tmp)
169 #undef tmp
170 AND (t, x)
171 ADD (acc, t)
172
173 //voice 4:
174 MOV (Ml, i2)
175 SWAP (Ml)
176 ANDI (Ml, 0xf0)
177 LSL (Ml)
178 LSL (Ml)
179 #define tmp Mh
180 MOV (tmp, i1)
181 LSR (tmp)
182 LSR (tmp)
183 OR (Ml, tmp)
184 #undef tmp
185 MOV (Mh, i3)
186 SWAP (Mh)
187 ANDI (Mh, 0xf0)
188 LSL (Mh)
189 LSL (Mh)
190 #define tmp _
191 MOV (tmp, i2)
192 LSR (tmp)
193 LSR (tmp)
194 OR (Mh, tmp)
195 #undef tmp
196 RCALL mod3();
197 SUB (t, n)
198 NEG (t)
199 SUBI (t, -8)
200 LDI (o, 1)
201 RCALL g();
202 MOV (x, s)
203 INC (x)
204 #define tmp o
205 MOV (tmp, x)
206 LSR (tmp)
207 ADD (tmp, x)
208 ROR (tmp)
209 LSR (tmp)
210 LSR (tmp)
211 ADD (tmp, x)
212 ROR (tmp)
213 ADD (tmp, x)
214 ROR (tmp)
215 LSR (tmp)
216 LSR (tmp)
217 MOV (x, tmp)
218 #undef tmp
219 AND (t, x)
220 ADD (acc, t)
221
222 putchar(acc<<4); //TODO
223 SUBI (i0, -1)
224 ADC (i1, zero, !i0)
225 ADC (i2, zero, !i0&&!i1)
226 ADC (i3, zero, !i0&&!i1&&!i2)
227 }
228 }
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