new version
[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero;
10 u8 i0;
11 u8 i1;
12 u8 i2;
13 u8 i3;
14 u8 x;
15 u8 t;
16 u8 o;
17 u8 _;
18 void g(void) {
19 // g(i, x, t, o) -> t
20 #define tmp _
21 ANDI (t, 0x07)
22 MOV (tmp, i2)
23 ANDI (tmp, 3)
24 TST (tmp)
25 #undef tmp
26 BREQ (skip)
27 SUBI (t, -8)
28 skip:
29 t = data[t];
30 /*MOV X_hi==_, data_hi
31 MOV X_lo==t, data_lo
32 ADD X_lo, t
33 CLR zero
34 ADC X_hi, zero
35 LD t, X */
36 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
37 t >>= o; //NOTE: o == {1, 2, 4}
38 AND (t, x)
39 ANDI (t, 3)
40 RET
41 };
42
43 int main(void) {
44 u8 n;
45 u8 s;
46 u8 acc;
47 //TODO: clear all vars/registers
48 for (;;) {
49 MOV (n, i2)
50 LSL (n)
51 LSL (n)
52 #define tmp acc
53 MOV (tmp, i1)
54 SWAP (tmp)
55 ANDI (tmp, 0x0f)
56 LSR (tmp)
57 LSR (tmp)
58 OR (n, tmp)
59 #undef tmp
60 MOV (s, i3)
61 ROR (s)
62 ROR (s)
63 ANDI (s, 0x80)
64 #define tmp acc
65 MOV (tmp, i2)
66 LSR (tmp)
67 OR (s, tmp)
68 #undef tmp
69
70 //voice 1:
71 LDI (x, 1)
72 MOV (t, n)
73 LDI (o, 4)
74 RCALL g();
75 MOV (acc, t)
76
77 //voice 2:
78 MOV (x, s)
79 #define tmp o
80 MOV (tmp, i2)
81 LSL (tmp)
82 LSL (tmp)
83 LSL (tmp)
84 MOV (t, i1)
85 SWAP (t)
86 ANDI (t, 0xf)
87 LSR (t)
88 OR (t, tmp)
89 #undef tmp
90 EOR (t, n)
91 LDI (o, 2)
92 RCALL g();
93 ADD (acc, t)
94
95 //voice 3:
96 MOV (x, s)
97 INC (x)
98 #define tmp o
99 MOV (tmp, x)
100 LSR (tmp)
101 LSR (tmp)
102 ADD (tmp, x)
103 ROR (tmp)
104 LSR (tmp)
105 ADD (tmp, x)
106 ROR (tmp)
107 LSR (tmp)
108 ADD (tmp, x)
109 ROR (tmp)
110 LSR (tmp)
111 MOV (x, tmp)
112 #undef tmp
113 t = ((i3&0x01)<<13 | i2<<5 | i1>>3) % 3; //TODO
114 ADD (t, n)
115 LDI (o, 2)
116 RCALL g();
117 ADD (acc, t)
118
119 //voice 4:
120 MOV (x, s)
121 INC (x)
122 #define tmp o
123 MOV (tmp, x)
124 LSR (tmp)
125 ADD (tmp, x)
126 ROR (tmp)
127 LSR (tmp)
128 LSR (tmp)
129 ADD (tmp, x)
130 ROR (tmp)
131 ADD (tmp, x)
132 ROR (tmp)
133 LSR (tmp)
134 LSR (tmp)
135 MOV (x, tmp)
136 #undef tmp
137 t = ((i3&0x01)<<14 | i2<<6 | i1>>2) % 3; //TODO
138 SUB (t, n)
139 NEG (t)
140 SUBI (t, -8)
141 LDI (o, 1)
142 RCALL g();
143 ADD (acc, t)
144
145 putchar(acc<<4);
146 #define tmp acc
147 CLR (tmp) //NOTE: maybe use dedicated zero register?
148 SUBI (i0, -1)
149 ADC (i1, tmp, !i0)
150 ADC (i2, tmp, !i0&&!i1)
151 ADC (i3, tmp, !i0&&!i1&&!i2)
152 #undef tmp
153 }
154 }
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