foo.c

   1 #include <stdio.h>
   2 #include "fakeasm.h"
   3 typedef unsigned char u8;
   4
   5 u8 data[] = {
   6         0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
   7         0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
   8 };
   9 u8 zero; //zero register
  10 u8 i0;
  11 u8 i1;
  12 u8 i2;
  13 u8 i3;
  14 u8 x;
  15 u8 t;
  16 u8 o;
  17 u8 _;
  18 #define Mh o //mod3 vars
  19 #define Ml t // -"-
  20 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
  21 void mod3(void) {
  22         // mod3(Mh.Ml) -> t
  23         #define tmp _
  24         ADD     (Ml, Mh)
  25         CLR     (Mh)
  26         ADC     (Mh, zero, carry) //Mh only holds the carry bit
  27         MOV     (tmp, Ml)
  28         SWAP    (tmp)
  29         ANDI    (tmp, 0x0f)
  30         SWAP    (Mh)
  31         OR      (tmp, Mh)
  32         ANDI    (Ml, 0x0f)
  33         ADD     (Ml, tmp)
  34         MOV     (tmp, Ml)
  35         LSR     (tmp)
  36         LSR     (tmp)
  37         ANDI    (Ml, 0x03)
  38         ADD     (Ml, tmp)
  39         MOV     (tmp, Ml)
  40         LSR     (tmp)
  41         LSR     (tmp)
  42         ANDI    (Ml, 0x03)
  43         ADD     (Ml, tmp)
  44         if (Ml > 2) Ml = Ml - 3; //TODO
  45         #undef tmp
  46 }
  47 void g(void) {
  48         // g(i, x, t, o) -> t
  49         #define tmp _
  50         ANDI    (t, 0x07)
  51         MOV     (tmp, i2)
  52         ANDI    (tmp, 3)
  53         TST     (tmp)
  54         #undef tmp
  55         BREQ    (skip)
  56         SUBI    (t, -8)
  57         skip:
  58         t = data[t];
  59         /*MOV X_hi==_, data_hi
  60           MOV X_lo==t, data_lo
  61           ADD X_lo, t
  62           ADC X_hi, zero
  63           LD  t, X         */
  64         t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
  65         t >>= o; //NOTE: o == {1, 2, 4}
  66         AND     (t, x)
  67         ANDI    (t, 3)
  68         RET
  69 };
  70
  71 int main(void) {
  72         u8 n;
  73         u8 s;
  74         u8 acc;
  75         //TODO: clear all vars/registers
  76         for (;;) {
  77                 MOV     (n, i2)
  78                 LSL     (n)
  79                 LSL     (n)
  80                 #define tmp acc
  81                 MOV     (tmp, i1)
  82                 SWAP    (tmp)
  83                 ANDI    (tmp, 0x0f)
  84                 LSR     (tmp)
  85                 LSR     (tmp)
  86                 OR      (n, tmp)
  87                 #undef tmp
  88                 MOV     (s, i3)
  89                 ROR     (s)
  90                 ROR     (s)
  91                 ANDI    (s, 0x80)
  92                 #define tmp acc
  93                 MOV     (tmp, i2)
  94                 LSR     (tmp)
  95                 OR      (s, tmp)
  96                 #undef tmp
  97
  98                 //voice 1:
  99                 LDI     (x, 1)
 100                 MOV     (t, n)
 101                 LDI     (o, 4)
 102                 RCALL   g();
 103                 MOV     (acc, t)
 104
 105                 //voice 2:
 106                 MOV     (x, s)
 107                 #define tmp o
 108                 MOV     (tmp, i2)
 109                 LSL     (tmp)
 110                 LSL     (tmp)
 111                 LSL     (tmp)
 112                 MOV     (t, i1)
 113                 SWAP    (t)
 114                 ANDI    (t, 0xf)
 115                 LSR     (t)
 116                 OR      (t, tmp)
 117                 #undef tmp
 118                 EOR     (t, n)
 119                 LDI     (o, 2)
 120                 RCALL   g();
 121                 ADD     (acc, t)
 122
 123                 //voice 3:
 124                 MOV     (x, s)
 125                 INC     (x)
 126                 #define tmp o
 127                 MOV     (tmp, x)
 128                 LSR     (tmp)
 129                 LSR     (tmp)
 130                 ADD     (tmp, x)
 131                 ROR     (tmp)
 132                 LSR     (tmp)
 133                 ADD     (tmp, x)
 134                 ROR     (tmp)
 135                 LSR     (tmp)
 136                 ADD     (tmp, x)
 137                 ROR     (tmp)
 138                 LSR     (tmp)
 139                 MOV     (x, tmp)
 140                 #undef tmp
 141                 Ml = i2<<5 | i1>>3;
 142                 Mh = i3<<5 | i2>>3;
 143                 RCALL   mod3();
 144                 ADD     (t, n)
 145                 LDI     (o, 2)
 146                 RCALL   g();
 147                 ADD     (acc, t)
 148
 149                 //voice 4:
 150                 MOV     (x, s)
 151                 INC     (x)
 152                 #define tmp o
 153                 MOV     (tmp, x)
 154                 LSR     (tmp)
 155                 ADD     (tmp, x)
 156                 ROR     (tmp)
 157                 LSR     (tmp)
 158                 LSR     (tmp)
 159                 ADD     (tmp, x)
 160                 ROR     (tmp)
 161                 ADD     (tmp, x)
 162                 ROR     (tmp)
 163                 LSR     (tmp)
 164                 LSR     (tmp)
 165                 MOV     (x, tmp)
 166                 #undef tmp
 167                 Ml = i2<<6 | i1>>2;
 168                 Mh = i3<<6 | i2>>2;
 169                 RCALL   mod3();
 170                 SUB     (t, n)
 171                 NEG     (t)
 172                 SUBI    (t, -8)
 173                 LDI     (o, 1)
 174                 RCALL   g();
 175                 ADD     (acc, t)
 176
 177                 putchar(acc<<4); //TODO
 178                 SUBI    (i0, -1)
 179                 ADC     (i1, zero, !i0)
 180                 ADC     (i2, zero, !i0&&!i1)
 181                 ADC     (i3, zero, !i0&&!i1&&!i2)
 182         }
 183 }