12 #define x r26 //==Xlo==Mh
13 #define t r27 //==Xhi==Ml
21 #define Mh r26 //mod3 vars
42 .byte 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58
43 .byte 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
46 .org 0x0000 ; RESET interrupt
48 .org 0x0008 ; TIM0_OVF interrupt
51 mod3: ; mod3(Mh.Ml) -> t
80 ; definitions to mul-tree readable:
83 .macro always _bit ; nop; for when a test() is not necessary (see tree)
85 .macro never _bit ; nop; for when a test() is not necessary (see tree)
87 .macro test _bit,_jmpto
91 .macro i_test _bit,_jmpto ; inverted test (for reordered 0x8_)
99 .macro shift8 ; top three bits don't need to be corrrect, so save cycles by not carrying
102 .macro shift0 ; nop; last shift is common
108 .macro add8 ; ditto with carrying
123 ;TODO: check correctness!
125 MOV tmp, t ; NOTE: must move value away from `t`, as that is also hi(X)
126 LDI Xhi, hi8(data) ; hi(data) always zero, but still need to clear the register
128 ADD Xlo, tmp ;<-- the offset (formerly `t`) into data[]
129 ;ADC Xhi, zero ; data == 0x40 t <= 0x10, so can never overflow
140 /* decision tree multiplication saves cycles and (hopefully) reduces code size
147 _?000 _?100 _?001 _?101
149 _0000 _1000 _0100 _1100 _1001 _0101 _1101
151 ... ... ... ... ... ... ...
153 B0 58 84 8C 69 75 9D */
170 RJMP end_mul ; calc'd 0xb0
172 m_1000: add16 $ shift16
181 RJMP end_mul ; calc'd 0x58
183 m__100: add16 $ shift16
195 RJMP end_mul ; calc'd 0x8c / 0x84
197 m____1: add16 $ shift16
203 m_1001: add16 $ shift16
212 RJMP end_mul ; calc'd 0x69
214 m__101: add16 $ shift16
225 RJMP end_mul ; calc'd 0x75
227 m_1101: add16 $ shift16
239 LSR a1 ;final shift is a common operation for all
241 MOV t, a1 ;;TODO: use a1 in main() directly
245 RET ; TODO: replace CALL/RET with IJMP?
247 main: ; setup routine
253 CLR acc ; we output a dummy sample before the actual first one
258 OUT SPL, x ; init stack ptr
260 OUT PUEB, zero ; disable pullups
262 OUT DDRB, x ; PORTB0:pwm, PORTB2:debug
264 OUT CCP, x ; change protected ioregs
265 OUT CLKPSR, one ; clock prescaler 1/2 (4Mhz)
266 OUT WDTCSR, zero; turn off watchdog ;;TODO: incomplete - see datasheet pg48
267 ; OUT SMCR, 2 ; sleep mode 'power down' ('idle' (default) has faster response time)
269 ;set timer/counter0 to 8bit fastpwm, non-inverting, no prescaler
274 OUT TIMSK0, one ; enable tim0_ovf
275 OUT TIFR0, one ; TODO: why?
281 SLEEP ; wait for interrupt
285 ; potential TODO: softcounter in r25 to only update duty cicle every n iterations
286 ; potential TODO: save/restore status register (SREG=0x3f) (only if something in mainloop)
288 OUT OCR0AL, acc ; start by outputting a sample, because routine has variable runtime
289 SBI PORTB, 2 ; to measure runtime
435 SWAP acc ; acc<<4, to be passed to OCR0AL
442 CBI PORTB, 2 ; end runtime measurement
443 ;TODO: to reduce jitter: clear pending tim0_ovf (TIFR0[TOV0] <- 1) ?
444 RETI ; reenables interrupts