10 #define x r24 //==a1==Mh
19 #define Ml r23 //mod3 vars
42 .org 0x0000 ; RESET interrupt
44 .org 0x0008 ; TIM0_OVF interrupt
48 .byte 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58
49 .byte 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
51 mod3: ; mod3(Mh.Ml) -> t
55 ADC Mh, Mh ; store carry in Mh
80 ; definitions to mul-tree readable:
83 .macro always _bit ; nop; for when a test() is not necessary (see tree)
85 .macro never _bit ; nop; for when a test() is not necessary (see tree)
87 .macro test _bit,_jmpto
91 .macro i_test _bit,_jmpto ; inverted test (for reordered 0x8_)
99 .macro shift8 ; top three bits don't need to be corrrect, so save cycles by not carrying
102 .macro shift0 ; nop; last shift is common
108 .macro add8 ; ditto with carrying
129 ;TODO: check correctness!
131 ADD Xlo, t ; NOTE: can't overflow, since RAMEND == 0x5F
136 /* decision tree multiplication saves cycles and (hopefully) reduces code size
143 _?000 _?100 _?001 _?101
145 _0000 _1000 _0100 _1100 _1001 _0101 _1101
147 ... ... ... ... ... ... ...
149 B0 58 84 8C 69 75 9D */
166 RJMP end_mul ; calc'd 0xb0
168 m_1000: add16 $ shift16
177 RJMP end_mul ; calc'd 0x58
179 m__100: add16 $ shift16
191 RJMP end_mul ; calc'd 0x8c / 0x84
193 m____1: add16 $ shift16
199 m_1001: add16 $ shift16
208 RJMP end_mul ; calc'd 0x69
210 m__101: add16 $ shift16
221 RJMP end_mul ; calc'd 0x75
223 m_1101: add16 $ shift16
235 LSR a1 ;final shift is a common operation for all
237 MOV t, a1 ;;TODO: use a1 in loop: directly
240 RET ; TODO: replace CALL/RET with IJMP?
242 main: ; setup routine
247 CLR acc ; we output a dummy sample before the actual first one
248 LDI Xhi, hi8(FLASHM + notes) ; never changes
254 OUT SPL, x ; init stack ptr
256 OUT PUEB, zero ; disable pullups
258 OUT DDRB, x ; PORTB0:pwm, PORTB2:debug
260 OUT CCP, x ; change protected ioregs
261 OUT CLKPSR, one ; clock prescaler 1/2 (4Mhz)
262 LDI x, 0xa7 ; determined by trial-and-error (->PORTB2)
263 OUT OSCCAL, x ; set oscillator calibration
264 OUT WDTCSR, zero; turn off watchdog ;;TODO: incomplete - see datasheet pg48
265 ; OUT SMCR, 2 ; sleep mode 'power down' ('idle' (default) has faster response time)
267 ;set timer/counter0 to 8bit fastpwm, non-inverting, no prescaler
272 OUT TIMSK0, one ; enable tim0_ovf
278 SLEEP ; wait for interrupt
282 ; potential TODO: softcounter in r25 to only update duty cicle every n iterations
283 ; potential TODO: save/restore status register (SREG=0x3f) (only if something in mainloop)
285 OUT OCR0AL, acc ; start by outputting a sample, because routine has variable runtime
286 SBI PORTB, 2 ; to measure runtime
432 SWAP acc ; acc<<4, to be passed to OCR0AL
439 CBI PORTB, 2 ; end runtime measurement
440 LDI _, 1 ; TODO: could use own register for speed
441 OUT TIFR0, _ ; clear pending interrupt (routine takes two intr.cycles)
442 RETI ; reenables interrupts