CLR (a2)
CLR (a1)
- switch(t) {
- case 0x58: // 0101 1000
+ CPI (t, 0x58)
+ BREQ (mul_58)
+ CPI (t, 0x69)
+ BREQ (mul_69)
+ CPI (t, 0x75)
+ BREQ (mul_75)
+ CPI (t, 0x84)
+ BREQ (mul_84)
+ CPI (t, 0x8c)
+ BREQ (mul_8c)
+ CPI (t, 0x9d)
+ BREQ (mul_9d)
+ CPI (t, 0xb0)
+ BREQ (mul_b0)
+ mul_58: // 0101 1000
LSR (a2)
ROR (a1)
LSR (a2)
ROR (a1)
LSR (a2)
ROR (a1)
- break;
- case 0x69: // 0110 1001
+ RJMP (endmul)
+ mul_69: // 0110 1001
ADD (a1, i0)
ADC (a2, i1, carry)
LSR (a2)
ROR (a1)
LSR (a2)
ROR (a1)
- break;
- case 0x75: // 0111 0101
+ RJMP (endmul)
+ mul_75: // 0111 0101
ADD (a1, i0)
ADC (a2, i1, carry)
LSR (a2)
ROR (a1)
LSR (a2)
ROR (a1)
- break;
- case 0x84: // 1000 0100
+ RJMP (endmul)
+ mul_84: // 1000 0100
LSR (a2)
ROR (a1)
LSR (a2)
ADC (a2, i1, carry)
LSR (a2)
ROR (a1)
- break;
- case 0x8c: // 1000 1100
+ RJMP (endmul)
+ mul_8c: // 1000 1100
LSR (a2)
ROR (a1)
LSR (a2)
ADC (a2, i1, carry)
LSR (a2)
ROR (a1)
- break;
- case 0x9d: // 1001 1101
+ RJMP (endmul)
+ mul_9d: // 1001 1101
ADD (a1, i0)
ADC (a2, i1, carry)
LSR (a2)
ADC (a2, i1, carry)
LSR (a2)
ROR (a1)
- break;
- case 0xb0: // 1011 0000
+ RJMP (endmul)
+ mul_b0: // 1011 0000
LSR (a2)
ROR (a1)
LSR (a2)
ADC (a2, i1, carry)
LSR (a2)
ROR (a1)
- }
+ endmul:
// end MUL
#undef a0