new version
[Chiptunes.git] / foo.c
diff --git a/foo.c b/foo.c
index ec0b8a5cf63853a708b33f58f8b3d334a5d9bbf5..c2bcb5d6c2d96651063ce533aae9b7c1f8f3ae57 100644 (file)
--- a/foo.c
+++ b/foo.c
@@ -64,94 +64,203 @@ void mul(void) { //don't need overhead of function (inline it)
        CLR     (a2)
        CLR     (a1)
 
-       #define MUL_ADD_ROR \
-               ADD     (a1, i0) \
-               ADC     (a2, i1, carry) \
-               MUL_ROR
+       CPI     (t, 0x58)
+       BREQ    (mul_58)
+       CPI     (t, 0x69)
+       BREQ    (mul_69)
+       CPI     (t, 0x75)
+       BREQ    (mul_75)
+       CPI     (t, 0x84)
+       BREQ    (mul_84)
+       CPI     (t, 0x8c)
+       BREQ    (mul_8c)
+       CPI     (t, 0x9d)
+       BREQ    (mul_9d)
+       CPI     (t, 0xb0)
+       BREQ    (mul_b0)
+       mul_58: // 0101 1000
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
 
-       #define MUL_ROR \
-               LSR     (a2) \
-               ROR     (a1) \
-               ROR     (t) //superfluous?
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               RJMP    (endmul)
+       mul_69: // 0110 1001
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
 
-       switch(t) {
-       case 0x58: // 0101 1000
-               MUL_ROR
-               MUL_ROR
-               MUL_ROR
-               MUL_ADD_ROR
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               RJMP    (endmul)
+       mul_75: // 0111 0101
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
 
-               MUL_ADD_ROR
-               MUL_ROR
-               MUL_ADD_ROR
-               MUL_ROR
-               break;
-       case 0x69: // 0110 1001
-               MUL_ADD_ROR
-               MUL_ROR
-               MUL_ROR
-               MUL_ADD_ROR
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               RJMP    (endmul)
+       mul_84: // 1000 0100
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
 
-               MUL_ROR
-               MUL_ADD_ROR
-               MUL_ADD_ROR
-               MUL_ROR
-               break;
-       case 0x75: // 0111 0101
-               MUL_ADD_ROR
-               MUL_ROR
-               MUL_ADD_ROR
-               MUL_ROR
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               RJMP    (endmul)
+       mul_8c: // 1000 1100
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
 
-               MUL_ADD_ROR
-               MUL_ADD_ROR
-               MUL_ADD_ROR
-               MUL_ROR
-               break;
-       case 0x84: // 1000 0100
-               MUL_ROR
-               MUL_ROR
-               MUL_ADD_ROR
-               MUL_ROR
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               RJMP    (endmul)
+       mul_9d: // 1001 1101
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
 
-               MUL_ROR
-               MUL_ROR
-               MUL_ROR
-               MUL_ADD_ROR
-               break;
-       case 0x8c: // 1000 1100
-               MUL_ROR
-               MUL_ROR
-               MUL_ADD_ROR
-               MUL_ADD_ROR
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               RJMP    (endmul)
+       mul_b0: // 1011 0000
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
 
-               MUL_ROR
-               MUL_ROR
-               MUL_ROR
-               MUL_ADD_ROR
-               break;
-       case 0x9d: // 1001 1101
-               MUL_ADD_ROR
-               MUL_ROR
-               MUL_ADD_ROR
-               MUL_ADD_ROR
-
-               MUL_ADD_ROR
-               MUL_ROR
-               MUL_ROR
-               MUL_ADD_ROR
-               break;
-       case 0xb0: // 1011 0000
-               MUL_ROR
-               MUL_ROR
-               MUL_ROR
-               MUL_ROR
-
-               MUL_ADD_ROR
-               MUL_ADD_ROR
-               MUL_ROR
-               MUL_ADD_ROR
-       }
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+               LSR (a2)
+               ROR (a1)
+               ADD (a1, i0)
+               ADC (a2, i1, carry)
+               LSR (a2)
+               ROR (a1)
+       endmul:
 
        // end MUL
        #undef a0
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