0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
};
-u8 zero; //zero register
-u8 i0;
-u8 i1;
-u8 i2;
-u8 i3;
-u8 x;
-u8 t;
-u8 o;
-u8 _;
-#define Mh o //mod3 vars
+u8 zero; //r16
+u8 acc; //r17
+u8 i0; //r18
+u8 i1; //r19
+u8 i2; //r20
+u8 i3; //r21
+u8 n; //r22
+u8 s; //r23
+u8 _; //r24
+u8 loop; //r25
+u8 t;/*==Ml*/ //r26 (Xlo)
+u8 x;/*==Mh*/ //r27 (Xhi)
+ //r28
+ //r29
+/*fakestack_l*/ //r30 (Zlo)
+/*fakestack_h*/ //r31 (Zhi)
+#define Mh x //mod3 vars
#define Ml t // -"-
//http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
void mod3(void) {
RET
#undef tmp
}
+void mul(void) { //don't need overhead of function (inline it)
+ // i1.i0 * t -> _.x.t
+ #define a1 x
+ #define a2 _
+ #define a0 t
+ // start MUL -- 92 cycles :( (unrolled and skipping second bit: 76)
+ CLR (a2)
+ CLR (a1)
+
+ CPI (t, 0x58)
+ BREQ (mul_58)
+ CPI (t, 0x69)
+ BREQ (mul_69)
+ CPI (t, 0x75)
+ BREQ (mul_75)
+ CPI (t, 0x84)
+ BREQ (mul_84)
+ CPI (t, 0x8c)
+ BREQ (mul_8c)
+ CPI (t, 0x9d)
+ BREQ (mul_9d)
+ CPI (t, 0xb0)
+ BREQ (mul_b0)
+ mul_58: // 0101 1000
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ RJMP (endmul)
+ mul_69: // 0110 1001
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ RJMP (endmul)
+ mul_75: // 0111 0101
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ RJMP (endmul)
+ mul_84: // 1000 0100
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ RJMP (endmul)
+ mul_8c: // 1000 1100
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ RJMP (endmul)
+ mul_9d: // 1001 1101
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ RJMP (endmul)
+ mul_b0: // 1011 0000
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ LSR (a2)
+ ROR (a1)
+ ADD (a1, i0)
+ ADC (a2, i1, carry)
+ LSR (a2)
+ ROR (a1)
+ endmul:
+
+ // end MUL
+ #undef a0
+ #undef a1
+ #undef a2
+ RET
+}
void g(void) {
- // g(i, x, t, o) -> t
+ // g(i, t) -> t
+ // tempvars: `x` and `_`
#define tmp _
ANDI (t, 0x07)
MOV (tmp, i2)
SUBI (t, -8)
skip:
t = data[t];
- /*MOV X_hi==_, data_hi
+ /*MOV X_hi==x, data_hi
MOV X_lo==t, data_lo
ADD X_lo, t
ADC X_hi, zero
LD t, X */
- t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
- t >>= o; //NOTE: o == {1, 2, 4}
- ANDI (t, 3)
- RET //TODO: CALL/RET is expensive; store PC in register and RJMP, then JRMP back
+ RCALL mul(); //stores used value in in x
+ MOV (t, x)
+ RET //TODO: replace CALL/RET with IJMP?
};
int main(void) {
- u8 n;
- u8 s;
- u8 acc;
- //TODO: clear all vars/registers
+ CLR (zero)
+ CLR (i0)
+ CLR (i1)
+ CLR (i2)
+ CLR (i3)
for (;;) {
MOV (n, i2)
LSL (n)
LSL (n)
- #define tmp acc
+ #define tmp _
MOV (tmp, i1)
SWAP (tmp)
ANDI (tmp, 0x0f)
OR (n, tmp)
#undef tmp
MOV (s, i3)
- ROR (s)
+ LSR (s)
ROR (s)
ANDI (s, 0x80)
- #define tmp acc
+ #define tmp _
MOV (tmp, i2)
LSR (tmp)
OR (s, tmp)
//voice 1:
MOV (t, n)
- LDI (o, 4)
RCALL g();
+ SWAP (t)
ANDI (t, 1)
MOV (acc, t)
//voice 2:
- #define tmp o
+ #define tmp _
MOV (tmp, i2)
LSL (tmp)
LSL (tmp)
OR (t, tmp)
#undef tmp
EOR (t, n)
- LDI (o, 2)
RCALL g();
+ LSR (t)
+ LSR (t)
+ ANDI (t, 3)
AND (t, s)
ADD (acc, t)
SWAP (Ml)
ANDI (Ml, 0xf0)
LSL (Ml)
- #define tmp Mh
+ #define tmp _
MOV (tmp, i1)
LSR (tmp)
LSR (tmp)
#undef tmp
RCALL mod3();
ADD (t, n)
- LDI (o, 2)
RCALL g();
+ LSR (t)
+ LSR (t)
+ ANDI (t, 3)
MOV (x, s)
INC (x)
- #define tmp o
+ #define tmp _
MOV (tmp, x)
LSR (tmp)
LSR (tmp)
ADD (tmp, x)
ROR (tmp)
LSR (tmp)
- MOV (x, tmp)
+ AND (t, tmp)
#undef tmp
- AND (t, x)
ADD (acc, t)
//voice 4:
- MOV (x, s)
- INC (x)
- #define tmp o
- MOV (tmp, x)
- LSR (tmp)
- ADD (tmp, x)
- ROR (tmp)
- LSR (tmp)
- LSR (tmp)
- ADD (tmp, x)
- ROR (tmp)
- ADD (tmp, x)
- ROR (tmp)
- LSR (tmp)
- LSR (tmp)
- MOV (x, tmp)
- #undef tmp
MOV (Ml, i2)
SWAP (Ml)
ANDI (Ml, 0xf0)
LSL (Ml)
LSL (Ml)
- #define tmp Mh
+ #define tmp _
MOV (tmp, i1)
LSR (tmp)
LSR (tmp)
SUB (t, n)
NEG (t)
SUBI (t, -8)
- LDI (o, 1)
RCALL g();
- AND (t, x)
+ LSR (t)
+ ANDI (t, 3)
+ INC (s)
+ #define tmp _
+ MOV (tmp, s)
+ LSR (tmp)
+ ADD (tmp, s)
+ ROR (tmp)
+ LSR (tmp)
+ LSR (tmp)
+ ADD (tmp, s)
+ ROR (tmp)
+ ADD (tmp, s)
+ ROR (tmp)
+ LSR (tmp)
+ LSR (tmp)
+ AND (t, tmp)
+ #undef tmp
ADD (acc, t)
putchar(acc<<4); //TODO
git://git.gir.st / Chiptunes.git / blobdiff