X-Git-Url: https://git.gir.st/Chiptunes.git/blobdiff_plain/3b86ca43b781401860999f0348ab9f03ee109567..e4f7baf085f9080e41d12d4a5166e3fde0135da5:/foo.c diff --git a/foo.c b/foo.c index 4d3cd18..c8eacff 100644 --- a/foo.c +++ b/foo.c @@ -6,58 +6,115 @@ u8 data[] = { 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58, 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58 }; +u8 i0; +u8 i1; +u8 i2; +u8 i3; u8 x; u8 t; u8 o; -u8 g(int i) { +void g(void) { + // g(i, x, t, o) -> t u8 tmp; ANDI (t, 0x07) - tmp = i >> 16; + MOV (tmp, i2) ANDI (tmp, 3) TST (tmp) BREQ (skip) SUBI (t, -8) skip: t = data[t]; - t = (i*t) >> o; + t = (((i1&0x1f)<<8|i0)*t) >> o; AND (t, x) ANDI (t, 3) - return t; + RET }; int main(void) { - int i; - unsigned short n; - unsigned short s; + u8 n; + u8 s; u8 acc; - for (i = 0;; i++) { - acc = 0; - n = i >> 14; - s = i >> 17; + //TODO: clear all vars/registers + for (;;) { + MOV (n, i2) + LSL (n) + LSL (n) + #define tmp acc + MOV (tmp, i1) + SWAP (tmp) + ANDI (tmp, 0x0f) + LSR (tmp) + LSR (tmp) + OR (n, tmp) + #undef tmp + MOV (s, i3) + ROR (s) + ROR (s) + ANDI (s, 0x80) + #define tmp acc + MOV (tmp, i2) + LSR (tmp) + OR (s, tmp) + #undef tmp //voice 1: LDI (x, 1) MOV (t, n) LDI (o, 12) - acc += g(i); + RCALL g(); + MOV (acc, t) //voice 2: MOV (x, s) - t = n ^ i >> 13; + #define tmp o + MOV (tmp, i2) + LSL (tmp) + LSL (tmp) + LSL (tmp) + MOV (t, i1) + SWAP (t) + ANDI (t, 0xf) + LSR (t) + OR (t, tmp) + #undef tmp + EOR (t, n) LDI (o, 10) - acc += g(i); + RCALL g(); + ADD (acc, t) //voice 3: - x = s / 3; - t = n + ((i >> 11) % 3); + MOV (x, s) + INC (x) + #define tmp o + x = (x*0x55)>>8; + #undef tmp + t = ((i3&0x01)<<13 | i2<<5 | i1>>3) % 3; + ADD (t, n) LDI (o, 10) - acc += g(i); + RCALL g(); + ADD (acc, t) //voice 4: - x = s / 5; - t = 8 + n - ((i >> 10) % 3); + MOV (x, s) + INC (x) + #define tmp o + x = (x*0x33)>>8; + #undef tmp + t = ((i3&0x01)<<14 | i2<<6 | i1>>2) % 3; + SUB (t, n) + NEG (t) + SUBI (t, -8) LDI (o, 9) - acc += g(i); + RCALL g(); + ADD (acc, t) + putchar(acc<<4); + #define tmp acc + LDI (tmp, 0) + SUBI (i0, -1) + ADC (i1, tmp, !i0) + ADC (i2, tmp, !i0&&!i1) + ADC (i3, tmp, !i0&&!i1&&!i2) + #undef tmp } }